Robotpkg Work In Progress
Fork from https://git.openrobots.org/robots/robotpkg.git
This is the official Low Side Synchronous Buck converter Gitlab
Code source of the Monte-Carlo Tree search, published at CP2021
A generator of Return-Oriented Programming on RISC-V
Build benchmark for RISC-V (default to RV64IMAC)
Cache side channel attacks for RISC-V (also works for x86)
Ethernet MAC 10/100Mbps IP (OpenCores) with AXI4 (Lite) interface.
Has Linux driver support.
Modification of RISC-V softcore processor Orca.
REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection.
Run on ML605 evaluation board with UART 115200.
Generate ROM with attacks for Rehad-Orca.
3D model of the Gerard Bauzil experimental room.
Bootloader (@6000_0000) that receive file from UART and write to DDR (@8000_0000)
Boot a 32-bit/64-bit RISC-V Linux!
With support for Matana kernel module.
For 32-bit target, the simulation with Spike or QEMU is broken, but works on real hardware. The Ethernet (opencores) support is for 32-bit only.