Explore projects
-
Updated
-
Archived 0Updated
-
Updated
-
Updated
-
Archived 0Updated
-
Updated
-
Updated
-
Updated
-
Updated
-
Updated
-
-
-
Modification of RISC-V softcore processor Orca.
REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.
Updated -
Generate ROM with attacks for Rehad-Orca.
For synthesis, place mem.hex in ip/idram/src/input. [Request GCC cross compiler (RV32IM).] For bitsteam, replace BRAM content of myorca.bit. [Request Xilinx ISE setup and liscence.]Updated -
Updated
-
Learning value function and warmstart policies.
Updated