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Modification of RISC-V softcore processor Orca.

REHAD: Using Low-Frequency Reconfigurable Hardware for Cache Side-Channel Attacks Detection. Run on ML605 evaluation board with UART 115200.

MATANA Implementation on Chipyard (Rocket-Chip RISC-V Softcore processor) on ML605 board

Livre d'introduction à ROS

Resource-Constrained Scheduling Solver based on difference logic and clause learning

This is the official Low Side Synchronous Buck converter Gitlab

Sample and basic use of LaTeX beamer theme

Cache side channel attacks for RISC-V (also works for x86)