Commits · master · MATANA / Benchmarks / Benchmark RISCV

Mar 03, 2022
- README: improve usage section · def24a95
  Yuxiao Mao authored 3 years ago
  
  def24a95
Sep 15, 2021
- README: adjust CPU_MHZ, dhrystone iter · 58f1c84b
  Yuxiao Mao authored 3 years ago
  
  58f1c84b
Sep 03, 2021
- Makefile: adjust CPU_MHZ, remove HZ from dhrystone cmd · 3cca7637
  Yuxiao Mao authored 3 years ago
  
  3cca7637
Aug 24, 2021
- Dhrystone: reduce iter number · 7761862d
  Yuxiao Mao authored 3 years ago
  
  7761862d
Aug 19, 2021
- Makefile: minor fix, add space · 3eafe062
  Yuxiao Mao authored 3 years ago
  
  3eafe062
- Makefile/README: move bench order to alphabetic · a43719de
  Yuxiao Mao authored 3 years ago
  
  a43719de
- Dhrystone: build, submodule, Makefile · 6375ccd3
  Yuxiao Mao authored 3 years ago
  
  6375ccd3
- Makefile: build and tips and clean for all benchs · 97c136cf
  Yuxiao Mao authored 3 years ago
  
  97c136cf
- NBench: build and submodule · 1b713e09
  Yuxiao Mao authored 3 years ago
  
  1b713e09
- HINT: build and submodule · 474a95bf
  Yuxiao Mao authored 3 years ago
  
  474a95bf
Aug 18, 2021
- STREAM: build and submodule · 31be9b59
  Yuxiao Mao authored 3 years ago
  
  31be9b59
Aug 06, 2021
- Embench-IOT: build and submodule · 927ab5bb
  Yuxiao Mao authored 3 years ago
  
  927ab5bb
Aug 03, 2021
- Submodule: add CoreMark, CoreMark-PRO as submodule · 31d52b73
  Yuxiao Mao authored 3 years ago
  
  31d52b73
- Init commit: benchmark build for riscv, CoreMark, CoreMark-PRO · 641ac9fa
  Yuxiao Mao authored 3 years ago
  
  641ac9fa