Unexpected triggering behaviour of ADC
When flashing the code of the main branch of the project, and observing the current signals, it appears that the ADC is only triggered once every 10 periods, instead of every 3 periods.
I1_low in blue and I2_low in red, the ADC acquisitions cause big drops in the signals.
This is caused by a postscaler located in owntech_hrtim_driver/zephyr/src/hrtim_voltage_mode.c on line 494 which is currently set on 9 which cause the ADC to be triggered once every 10 periods (the postscaler start at 0).