[Power] Half-bridge power stage layout
Following a discussion we had during a hackathon in Paris, we encountered a valid argument regarding the actual power stage layout.
The finding is the inductive power loop is not currently minimized properly.
The return path on the ground plane going to the high frequency capacitor is currently not short enough. The length of the loop prevent any realistic action from the decoupling capacitor in the current layout.
None of the ground planes in the internal or external layers provide direct connection between GNDREF of the low mosfet and the GNDREF connection of the decoupling capacitor. The current design tried to maximize passive cooling through large extern and intern switching nodes planes connected with vias that prevent any direct return current loop. As such, it minimize thermal issues but maximize parasitic inductance in the power loop.
The following video link provide good advices for half-bridge power stage optimal layout https://www.youtube.com/watch?v=wm2Hp4DXIf0