- 12 Jul, 2021 1 commit
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Yuxiao Mao authored
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- 08 Jul, 2021 3 commits
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Yuxiao Mao authored
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Yuxiao Mao authored
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Yuxiao Mao authored
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- 07 Jul, 2021 1 commit
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Yuxiao Mao authored
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- 06 Jul, 2021 1 commit
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Yuxiao Mao authored
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- 05 Jul, 2021 3 commits
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Yuxiao Mao authored
DetectPrime: move some const to params, rename last_* to saved*, rename page to tag to be more accurate
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Yuxiao Mao authored
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Yuxiao Mao authored
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- 01 Jul, 2021 2 commits
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Yuxiao Mao authored
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Yuxiao Mao authored
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- 30 Jun, 2021 1 commit
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Yuxiao Mao authored
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- 29 Jun, 2021 6 commits
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Yuxiao Mao authored
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Yuxiao Mao authored
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Yuxiao Mao authored
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Yuxiao Mao authored
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Yuxiao Mao authored
Detect: merge TT+TF into the same file as they are based basically on the same pattern. Update RegmapUtil to include event/threshold/alarm and simplify regmap creation for attacks
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Yuxiao Mao authored
Detect: patternTT add valid signal, add inst isLoad, add Simple Prime DCache detection pattern, rename MatanaDecode to RocketDecode
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- 28 Jun, 2021 1 commit
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Yuxiao Mao authored
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- 27 Jun, 2021 4 commits
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Yuxiao Mao authored
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Yuxiao Mao authored
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Yuxiao Mao authored
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Yuxiao Mao authored
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- 25 Jun, 2021 4 commits
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Yuxiao Mao authored
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Yuxiao Mao authored
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Yuxiao Mao authored
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Yuxiao Mao authored
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- 24 Jun, 2021 2 commits
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Yuxiao Mao authored
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Yuxiao Mao authored
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- 23 Jun, 2021 2 commits
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Yuxiao Mao authored
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Yuxiao Mao authored
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- 21 Jun, 2021 1 commit
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Yuxiao Mao authored
Merge branch 'dev': add pc/addrmem input, add procNum/resetCounters control reg, fix timerh double detection
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- 25 Feb, 2021 1 commit
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Yuxiao Mao authored
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- 24 Feb, 2021 1 commit
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Yuxiao Mao authored
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- 23 Feb, 2021 3 commits
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Yuxiao Mao authored
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Yuxiao Mao authored
RehadIO: add pc and addrmem to Rehad IO (extract from Core, not connected to Sync yet), rename tile_rehad by rehad_tile
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Yuxiao Mao authored
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- 22 Feb, 2021 2 commits
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Yuxiao Mao authored
RehadDetection: remove 'h' inst in timer detection to reduce false positive, as high and low timer inst are often call together
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Yuxiao Mao authored
RehadSync: add comment for rehadXdirect (no need AsyncQueue), add val log2ClockDiv, add init to seq2par reg
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- 19 Feb, 2021 1 commit
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Yuxiao Mao authored
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