Detect: patternTT add valid signal, add inst isLoad, add Simple Prime DCache detection pattern, rename MatanaDecode to RocketDecode

Merge branch 'dev': add pc/addrmem input, add procNum/resetCounters control reg, fix timerh double detection

RehadIO: add pc and addrmem to Rehad IO (extract from Core, not connected to Sync yet), rename tile_rehad by rehad_tile

RehadDetection: remove 'h' inst in timer detection to reduce false positive, as high and low timer inst are often call together

RehadSync: add comment for rehadXdirect (no need AsyncQueue), add val log2ClockDiv, add init to seq2par reg

Cache: return to original Med Core settings (64 sets x 1 way), add trick patch to L2 allow Xilinx ISE use BlockRAM insteed of LUT

This is done by adding a custom WB classic 2 AXI4 bridge (no err signal handling). On board Linux and FTP ok.
Unfortunately it did not really improve Ethernet speed (always 5KiB/s), but it did remove 'RX Overrun' warning.

(Ethernet MAC is an IP Core of OpenCores, WB2AXIP is an IP Core of ZipCPU.)

EthernetAXI4: try to fix eth master interface, but perhaps it works already. tested in simulation post-translate