Commit f894d5e6 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

clkgen: remove reset (was hw_reset), and clockdiv use only 2 shiftreg now, sim Xilinx reset ok

parent e90b32c0
......@@ -168,8 +168,7 @@ module BoardTop_bram
clkwiz_200_50 clkgen (
.CLK_IN200_P(hw_clk200m_p),
.CLK_IN200_N(hw_clk200m_n),
.CLK_OUT50(clock),
.RESET(hw_reset)
.CLK_OUT50(clock)
);
// Sync reset
......
......@@ -64,15 +64,13 @@
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clkwiz_200_50,clk_wiz_v3_3,{component_name=clkwiz_200_50,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
(* CORE_GENERATION_INFO = "clkwiz_200_50,clk_wiz_v3_3,{component_name=clkwiz_200_50,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module clkwiz_200_50
(// Clock in ports
input CLK_IN200_P,
input CLK_IN200_N,
// Clock out ports
output CLK_OUT50,
// Status and control signals
input RESET
output CLK_OUT50
);
// Input buffering
......@@ -163,7 +161,7 @@ module clkwiz_200_50
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
.RST (1'b0));
// Output buffering
//-----------------------------------
......
......@@ -9,7 +9,7 @@ import freechips.rocketchip.util.{Pow2ClockDivider, ShiftRegInit}
// Adapt from rocket-chip.prci.ClockDivider
// Fix: param (x) to log2(x)
// Fix: Reset not set when reset is also clock's reset
// Fix: Reset is async for the slow domain
class RehadClockDivider(div: Int)(implicit p: Parameters) extends LazyModule {
require(isPow2(div))
......@@ -22,7 +22,7 @@ class RehadClockDivider(div: Int)(implicit p: Parameters) extends LazyModule {
val div_clock: Clock = Pow2ClockDivider(in.clock, log2Ceil(div))
out.clock := div_clock
out.reset := withClockAndReset(out.clock, in.reset.asAsyncReset) {
ShiftRegInit(in = false.B, n = 3, init = true.B, name = Some("slow_reset_pipe"))
ShiftRegInit(in = false.B, n = 2, init = true.B, name = Some("slow_reset_pipe"))
}
}
}
......
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