Commit ef4ee821 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

Merge branch 'dev': crossing with tilelink, interrupts, seq2par, gen Verilog ok with correctIO

parents abf37b25 da6f85f4
......@@ -5,3 +5,5 @@ version := "0.1"
name := "rehad"
scalaVersion := "2.12.4"
addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full)
......@@ -9,9 +9,10 @@ trait CanHavePeripheryRehad { this: chipyard.Subsystem =>
val rehad = p(RehadKey) match {
case Some(params) => {
val rehad = LazyModule(new TLRehadModule(params, pbus.beatBytes)(p))
pbus.toVariableWidthSlave(Some(portName)) { rehad.node }
val rehad = LazyModule(new RehadTopModule(params, pbus.beatBytes)(p))
pbus.toVariableWidthSlaveNode(Some(portName)) { rehad.node }
ibus.fromSync := rehad.intnode
rehad.clockdiv.node := pbus.clockNode
Some(rehad)
}
case None => None
......
......@@ -36,14 +36,14 @@ index 24be68b0b..c29b9cbfd 100644
/** Some other non-tilelink but still standard inputs */
diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala
index 118dc9a72..0af4bb545 100644
index 118dc9a72..cc2697035 100644
--- a/src/main/scala/tile/Core.scala
+++ b/src/main/scala/tile/Core.scala
@@ -133,5 +133,6 @@ trait HasCoreIO extends HasTileParameters {
val cease = Bool().asOutput
val wfi = Bool().asOutput
val traceStall = Bool().asInput
+ val rehad = new RehadCoreIO()
+ val rehad = new RehadCoreIO
}
}
diff --git a/src/main/scala/tile/Rehad.scala b/src/main/scala/tile/Rehad.scala
......
package rehad
import chisel3._
import chisel3.experimental.chiselName
import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.regmapper.{HasRegMap, RegField, RegFieldDesc}
import freechips.rocketchip.tile.{XLen, RehadCoreIO}
import freechips.rocketchip.tilelink.{TLRegisterRouter, TLRegBundle, TLRegModule}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.prci.{ClockDivider, ClockSinkDomain}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc}
import freechips.rocketchip.tile.{RehadCoreIO}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
object RehadControlReg {
val rtest = 0x00
......@@ -14,16 +18,19 @@ object RehadControlReg {
val ie = 0x0C
}
trait RehadTopIO extends Bundle {
val params: RehadParams
case class RehadTopIO(params: RehadParams) extends Bundle {
val tiles = Vec(params.nHarts, Flipped(new RehadCoreIO))
}
trait RehadModule extends HasRegMap {
val params: RehadParams
implicit val p: Parameters
val io: RehadTopIO
val interrupts: Vec[Bool]
class RehadSlowDetectionImp(outer: RehadSlowDetection, params: RehadParams)
extends LazyModuleImp(outer)
{
val io = IO(new Bundle {
val pack = Vec(params.clockDiv, Flipped(new RehadCoreIO()))
})
val interrupts = if (outer.intnode.out.isEmpty) Vec(0, Bool()) else outer.intnode.out(0)._1
def regmap(mapping: RegField.Map*) = outer.node.regmap(mapping:_*)
// RegMap
val counterSize = params.counterWidth
......@@ -31,7 +38,7 @@ trait RehadModule extends HasRegMap {
val civalid = RegInit(0.U(counterSize.W))
val ciinst = RegInit(0.U(counterSize.W))
val ie = RegInit(false.B)
val core0 = io.tiles(0)
val core0 = io.pack(0)
when (core0.inst_valid) {
civalid := civalid + 1.U
......@@ -54,11 +61,68 @@ trait RehadModule extends HasRegMap {
)
}
class TLRehadModule(params: RehadParams, beatBytes: Int)(implicit p: Parameters)
extends TLRegisterRouter(
params.address, "rehad", Seq("laas,rehad"),
interrupts = 1,
beatBytes = beatBytes)(
new TLRegBundle(params, _) with RehadTopIO)(
new TLRegModule(params, _, _) with RehadModule)
// ? Unable to automatically infer cloneType on class TLRehadModule
class RehadSlowDetection(params: RehadParams, beatBytes: Int)(implicit p: Parameters)
extends LazyModule
{
lazy val module = new RehadSlowDetectionImp(this, params)
// tilelink
val device = new SimpleDevice("rehad", Seq("laas,rehad"))
val node = TLRegisterNode(
address = Seq(AddressSet(params.address, 0xfff)),
device = device,
beatBytes = beatBytes)
val intnode = IntSourceNode(
IntSourcePortSimple(
num = 1,
resources = Seq(Resource(device, "int"))))
}
@chiselName
class RehadTopModuleImp(outer: RehadTopModule, params: RehadParams)
extends LazyModuleImp(outer)
{
val io = IO(new RehadTopIO(params))
val slow = outer.rehad_slow_domain.module
val detection = outer.rehad_slow_detection.module
detection.clock := slow.clock
detection.reset := slow.reset
val par0 = RehadUtil.seq2par(params.clockDiv, io.tiles(0))
// Registered at slow side
withClock(slow.clock) {
val par0reg = RegNext(par0)
detection.io.pack := par0reg
}
}
class RehadTopModule(params: RehadParams, beatBytes: Int)(implicit p: Parameters)
extends LazyModule
with HasClockDomainCrossing
{
lazy val module = new RehadTopModuleImp(this, params)
// Detection Module
val rehad_slow_detection = LazyModule(new RehadSlowDetection(params, beatBytes))
// Clock divider and slow clock domain
val clockdiv = LazyModule(new ClockDivider(params.clockDiv))
val rehad_slow_domain = LazyModule(new ClockSinkDomain(take = None))
rehad_slow_domain.clockNode := clockdiv.node
// TileLink with crossing
val node = TLInwardCrossingHelper("rehadXnode", rehad_slow_domain, rehad_slow_detection.node)(RationalCrossing(FastToSlow))
val intnode = IntOutwardCrossingHelper("rehadXint", rehad_slow_domain, rehad_slow_detection.intnode)(RationalCrossing(FastToSlow))
}
object RehadUtil {
// Sequential to parallel logic, with most recent signal (input) at Vec(0)
def seq2par[T <: Data](clockDiv: Int, gen: T) : Vec[T] = {
val par = Reg(Vec(clockDiv, chiselTypeOf(gen)))
par.foldLeft(gen) { case (i, next) => {
next := i
next
}}
par
}
}
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