Commit e02301c9 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

CacheEvents: add mem access event (from instruction), remove miss-N

parent b252a881
......@@ -52,4 +52,15 @@ class AnalyzeInst()(implicit mp: MatanaParams) extends MemoryOpConstants {
// Jump: any jump including br, jal, jalr
val isJump = Wire(Bool())
isJump := in.valid && (ctrlsig.branch || ctrlsig.jal || ctrlsig.jalr)
// MemRW : memory read or write, according to Consts.isRead/isWrite
val isMemRW = Wire(Bool())
isMemRW := in.valid && (
ctrlsig.mem_cmd === M_XRD || ctrlsig.mem_cmd === M_XLR || ctrlsig.mem_cmd === M_XSC ||
ctrlsig.mem_cmd === M_XWR || ctrlsig.mem_cmd === M_PWR || ctrlsig.mem_cmd === M_XSC ||
isAMO(ctrlsig.mem_cmd) )
// MemLoadStore : memory load or store
val isMemLS = Wire(Bool())
isMemLS := in.valid && (ctrlsig.mem_cmd === M_XRD || ctrlsig.mem_cmd === M_XWR)
}
......@@ -12,6 +12,8 @@ class DetectPatternCacheEventIn()(implicit val mp: MatanaParams) extends Bundle
val isMonitoring = Bool()
val pack_has_valid = Bool()
val vec_hpc = Vec(mp.clockDiv, new MatanaCoreHpcIO())
val pack_has_memrw = Bool()
val pack_has_memls = Bool()
}
class DetectPatternCacheEvent()(implicit mp: MatanaParams) {
......@@ -24,7 +26,7 @@ class DetectPatternCacheEventInternal(params: DetectPatternCacheEventParams)(imp
// Attack pattern
// Description: a high rate of Data cache miss / instruction
// -) Count pack_has_dcache_miss event (as count the exact value is difficult)
// N) = atk_dcache_miss, but decrement by 1 if count_pack_valid reach thresh X
// N) = atk_dcache_miss, but decrement by 1
val pack_has_dcache_miss = RegInit(false.B).suggestName("dpdcacheevent_pack_has_dcache_miss")
pack_has_dcache_miss := in.vec_hpc.map(_.dcache_miss).reduce(_||_)
......@@ -32,32 +34,6 @@ class DetectPatternCacheEventInternal(params: DetectPatternCacheEventParams)(imp
val atk_dcache_miss = RegInit(false.B)
atk_dcache_miss := pack_has_dcache_miss && in.isMonitoring
// Count pack valid for decrement counters
val count_pack_valid = RegInit(0.U(mp.counterWidth.W)).suggestName("dpdcacheevent_count_pack_valid")
when (in.resetCounters) {
count_pack_valid := 0.U
}.elsewhen (in.isMonitoring) {
count_pack_valid := count_pack_valid + in.pack_has_valid
}
val countPackValidThreshLengthMinus1_1 = 2 // Thresh = 2^(2+1) = 8 = 0x8 (0b000)
val countPackValidThreshLengthMinus1_2 = 4 // Thresh = 2^(4+1) = 32 = 0x20
val countPackValidThreshLengthMinus1_3 = 6 // Thresh = 2^(6+1) = 128 = 0x80
val countPackValidThreshLengthMinus1_4 = 8 // Thresh = 2^(8+1) = 512 = 0x200
val countPackValidThreshLengthMinus1_5 = 10 // Thresh = 2^(10+1) = 2048 = 0x800
val atk_dcache_miss_dec1 = RegInit(false.B)
atk_dcache_miss_dec1 := count_pack_valid(countPackValidThreshLengthMinus1_1, 0) === 0.U && in.isMonitoring
val atk_dcache_miss_dec2 = RegInit(false.B)
atk_dcache_miss_dec2 := count_pack_valid(countPackValidThreshLengthMinus1_2, 0) === 0.U && in.isMonitoring
val atk_dcache_miss_dec3 = RegInit(false.B)
atk_dcache_miss_dec3 := count_pack_valid(countPackValidThreshLengthMinus1_3, 0) === 0.U && in.isMonitoring
val atk_dcache_miss_dec4 = RegInit(false.B)
atk_dcache_miss_dec4 := count_pack_valid(countPackValidThreshLengthMinus1_4, 0) === 0.U && in.isMonitoring
val atk_dcache_miss_dec5 = RegInit(false.B)
atk_dcache_miss_dec5 := count_pack_valid(countPackValidThreshLengthMinus1_5, 0) === 0.U && in.isMonitoring
// Other events
val pack_has_dcache_blocked = RegInit(false.B).suggestName("dpdcacheevent_pack_has_dcache_blocked")
pack_has_dcache_blocked := in.vec_hpc.map(_.dcache_blocked).reduce(_||_) && in.isMonitoring
......@@ -73,11 +49,8 @@ class DetectPatternCacheEventInternal(params: DetectPatternCacheEventParams)(imp
override def regmap(offset: Int) =
RegmapUtil.countEvent(atk_dcache_miss, in.resetCounters, offset, "AtkDCacheEventMiss") ++
RegmapUtil.countEventMax(atk_dcache_miss, in.resetCounters, atk_dcache_miss_dec1, offset + 0x10, "AtkDCacheEventMiss1") ++
RegmapUtil.countEventMax(atk_dcache_miss, in.resetCounters, atk_dcache_miss_dec2, offset + 0x18, "AtkDCacheEventMiss2") ++
RegmapUtil.countEventMax(atk_dcache_miss, in.resetCounters, atk_dcache_miss_dec3, offset + 0x20, "AtkDCacheEventMiss3") ++
RegmapUtil.countEventMax(atk_dcache_miss, in.resetCounters, atk_dcache_miss_dec4, offset + 0x28, "AtkDCacheEventMiss4") ++
RegmapUtil.countEventMax(atk_dcache_miss, in.resetCounters, atk_dcache_miss_dec5, offset + 0x30, "AtkDCacheEventMiss5") ++
RegmapUtil.countEvent(in.pack_has_memrw, in.resetCounters, offset + 0x40, "PackMemRW") ++
RegmapUtil.countEvent(in.pack_has_memls, in.resetCounters, offset + 0x44, "PackMemLS") ++
RegmapUtil.countEvent(pack_has_dcache_blocked, in.resetCounters, offset + 0x80, "PackDCacheBlocked") ++
RegmapUtil.countEvent(pack_has_dcache_release, in.resetCounters, offset + 0x84, "PackDCacheRelease") ++
RegmapUtil.countEvent(pack_has_branch_mispredict, in.resetCounters, offset + 0x88, "PackBranchMispredict") ++
......
......@@ -100,7 +100,7 @@ class MatanaSlowDetectionImp(outer: MatanaSlowDetection, params: MatanaParams)
// Analysis result of each instruction in the current pack
Seq(valid,
aInst.isTimer, aInst.isFlushL1D, aInst.isLoadWord, aInst.isJalr,
aInst.isJump)
aInst.isJump, aInst.isMemRW, aInst.isMemLS)
}
// If at least one instruction has the instruction pattern in pack
......@@ -110,6 +110,8 @@ class MatanaSlowDetectionImp(outer: MatanaSlowDetection, params: MatanaParams)
val pack_has_loadword = RegInit(false.B)
val pack_has_jalr = RegInit(false.B)
val pack_has_jump = RegInit(false.B)
val pack_has_memrw = RegInit(false.B)
val pack_has_memls = RegInit(false.B)
// when isMonitoring, return actual value
pack_has_valid := Mux(isMonitoring, pack_analysis.map(_(0)).reduce(_||_), false.B)
pack_has_timer := Mux(isMonitoring, pack_analysis.map(_(1)).reduce(_||_), false.B)
......@@ -117,6 +119,8 @@ class MatanaSlowDetectionImp(outer: MatanaSlowDetection, params: MatanaParams)
pack_has_loadword := Mux(isMonitoring, pack_analysis.map(_(3)).reduce(_||_), false.B)
pack_has_jalr := Mux(isMonitoring, pack_analysis.map(_(4)).reduce(_||_), false.B)
pack_has_jump := Mux(isMonitoring, pack_analysis.map(_(5)).reduce(_||_), false.B)
pack_has_memrw := Mux(isMonitoring, pack_analysis.map(_(6)).reduce(_||_), false.B)
pack_has_memls := Mux(isMonitoring, pack_analysis.map(_(7)).reduce(_||_), false.B)
//--------------------------------------------------------------
......@@ -152,6 +156,8 @@ class MatanaSlowDetectionImp(outer: MatanaSlowDetection, params: MatanaParams)
detectPatternCacheEvent.in.isMonitoring := isMonitoring
detectPatternCacheEvent.in.pack_has_valid := pack_has_valid
detectPatternCacheEvent.in.vec_hpc := pack0.vec_hpc
detectPatternCacheEvent.in.pack_has_memrw := pack_has_memrw
detectPatternCacheEvent.in.pack_has_memls := pack_has_memls
// Test PC
val lastPC = RegInit(0.U(mp.addrWidth.W))
......
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