Commit cc0664b9 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

Detect: add some comment on todo and pattern description

parent 8b09fe7c
......@@ -25,7 +25,7 @@ class DetectExample()(implicit mp: MatanaParams) {
class DetectExampleInternal(params: DetectExampleParams)(implicit mp: MatanaParams) extends DetectExample {
// Logic that detect the attack
val atk_example = Wire(Bool())
val atk_example = Wire(Bool()) // or RegInit(false.B) to reduce circuit complexity
atk_example := in.some_atk && in.isMonitoring
// The regmap for bus
......
......@@ -40,6 +40,11 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
// fdc42783 lw a5,-36(s0)
// The use of LD / LW is important in order to load an 32-bit+ address value, if use LH / LB then futher manipulation are needed
// Use of this pattern in addition of Timer pattern:
// 1) Proof of concept of memory access based detection
// 2) When the attacker use other means to time measurement (other than instruction, for example)
// 3) Detection of attacks which did not need time measurement (rowhammer, performance degratation attack)
// Attack pattern
// Description: Multiples access to DCache, each time in same set with differents tag
......@@ -103,7 +108,7 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
atk_prime_2 := (count2 === countThresh2.U) && in.isMonitoring && in.dmemaddr_valid
// Attack Pattern
// Attack Pattern (instruction-based)
// Description: all valid pack contains an word size load. For -O0 there is store with load, we suppose if store to the same addr, the next load can be conclude in the same slow cycle.
// 1) valid load c+1, valid not load c-2 (thresh 16)
......@@ -125,8 +130,7 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
// Attack Pattern
// Description: Mix pattern
// 1) count1, but decrement the counter by 1 if count_pack_valid reach thresh (0x800=2048)
// => TODO: perhaps adjust using dmemaddr / slow cycle count
// 1) count1, but decrement the counter by 1 if count_pack_valid reach thresh (0x800=2048) // TODO: perhaps adjust using dmemaddr / slow cycle count
val countPackValidThresh = 0x800L //2048
val count_pack_valid = RegInit(0.U(mp.counterWidth.W)).suggestName("dpprime_count_pack_valid")
......
......@@ -25,6 +25,7 @@ class RegmapUtilCountEvent(regName: String)(implicit mp: MatanaParams) {
val threshEvent = RegInit(0.U(mp.counterWidth.W)).suggestName("thresh" + regName)
// TODO: better raise alarmEvent the same cycle that countEvent reach threshEvent?
val alarmEvent = RegInit(false.B).suggestName("alarm" + regName)
when ((threshEvent =/= 0.U) && (countEvent >= threshEvent)) {
alarmEvent := true.B
......
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