Commit cbbd5b17 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

Prime: mix change based on pack valid to slow cycle

parent 6363fcc0
......@@ -195,20 +195,20 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
// 2) = atk_prime_1, but decrement the counter by 1 if count_pack_valid reach thresh 0x400 (1024)
// Count pack valid for decrement counters
val count_pack_valid = RegInit(0.U(mp.counterWidth.W)).suggestName("dpprime_count_pack_valid")
val count_slow_cycle = RegInit(0.U(mp.counterWidth.W)).suggestName("dpprime_count_pack_valid")
when (in.resetCounters) {
count_pack_valid := 0.U
count_slow_cycle := 0.U
}.elsewhen (in.isMonitoring) {
count_pack_valid := count_pack_valid + in.pack_has_valid
count_slow_cycle := count_slow_cycle + 1.U
}
val countPackValidThreshLengthMinus1_1 = 10 // Thresh = 2^(10+1) = 2048 = 0x800
val countPackValidThreshLengthMinus1_2 = 9 // Thresh = 2^(9+1) = 1024 = 0x400
val countSlowCycleThreshLengthMinus1_1 = 10 // Thresh = 2^(10+1) = 2048 = 0x800
val countSlowCycleThreshLengthMinus1_2 = 9 // Thresh = 2^(9+1) = 1024 = 0x400
val atk_prime_mix1_dec = RegInit(false.B)
atk_prime_mix1_dec := count_pack_valid(countPackValidThreshLengthMinus1_1, 0) === 0.U
atk_prime_mix1_dec := count_slow_cycle(countSlowCycleThreshLengthMinus1_1, 0) === 0.U
val atk_prime_mix2_dec = RegInit(false.B)
atk_prime_mix2_dec := count_pack_valid(countPackValidThreshLengthMinus1_2, 0) === 0.U
atk_prime_mix2_dec := count_slow_cycle(countSlowCycleThreshLengthMinus1_2, 0) === 0.U
// Debug Signals
......
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