Commit c37bffea authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

MatanaTop: adapt to no frequency difference connection (synchrone)

parent f134d3f4
......@@ -11,7 +11,7 @@ import freechips.rocketchip.util.{Pow2ClockDivider, ShiftRegInit}
// Fix: param (x) to log2(x)
// Fix: Reset is async for the slow domain
class MatanaClockDivider(log2Div: Int)(implicit p: Parameters) extends LazyModule {
require(log2Div > 0)
require(log2Div >= 0)
val node = ClockAdapterNode(
sourceFn = { case src => src.copy(give = src.give.map(x => x.copy(freqMHz = x.freqMHz / 2))) },
......
......@@ -26,10 +26,9 @@ class MatanaTopModule(params: MatanaParams, beatBytes: Int)(implicit p: Paramete
val matana_slow_domain = LazyModule(new ClockSinkDomain(take = None))
matana_slow_domain.clockNode := clockdiv.node
// TileLink and Interrupt crossing to slow clock domain
// Was RationalCrossing(SlowToFast), dont know if it is this element that cause Linux Kernel Freezing
val node = TLInwardCrossingHelper("matanaXbus", matana_slow_domain, matana_slow_detection.node)(AsynchronousCrossing())
val intnode = IntOutwardCrossingHelper("matanaXint", matana_slow_domain, matana_slow_detection.intnode)(AsynchronousCrossing())
// TileLink and Interrupt nodes, (optional) crossing to slow clock domain
val node = if (params.log2ClockDiv == 0) matana_slow_detection.node else TLInwardCrossingHelper("matanaXbus", matana_slow_domain, matana_slow_detection.node)(AsynchronousCrossing())
val intnode = if (params.log2ClockDiv == 0) matana_slow_detection.intnode else IntOutwardCrossingHelper("matanaXint", matana_slow_domain, matana_slow_detection.intnode)(AsynchronousCrossing())
}
@chiselName
......@@ -40,9 +39,27 @@ class MatanaTopModuleImp(outer: MatanaTopModule, params: MatanaParams)
val tiles = Vec(params.nHarts, Flipped(new MatanaCoreIO))
})
val slow = outer.matana_slow_domain.module
val detection = outer.matana_slow_detection.module
if (params.log2ClockDiv == 0) {
// Without frequency difference
io.tiles.zipWithIndex.map { case (tile, i) =>
// Call MatanaSync but is only for formatting
detection.io.packs(i).vec_inst_data := RegNext(MatanaSync.seq2par(1, tile.inst_data))
detection.io.packs(i).vec_inst_valid := RegNext(MatanaSync.seq2par(1, tile.inst_valid))
detection.io.packs(i).one_pc_data := RegNext(tile.pc_data)
detection.io.packs(i).one_pc_valid := RegNext(tile.pc_valid)
detection.io.packs(i).one_dmemaddr_data := RegNext(tile.dmemaddr_data)
detection.io.packs(i).one_dmemaddr_valid := RegNext(tile.dmemaddr_valid)
detection.io.packs(i).one_dmempaddr_data := RegNext(tile.dmempaddr_data)
detection.io.packs(i).one_dmempaddr_valid := RegNext(tile.dmempaddr_valid)
detection.io.packs(i).vec_hpc := RegNext(MatanaSync.seq2par(1, tile.hpc))
}
} else {
// With frequency difference
val slow = outer.matana_slow_domain.module
// Detection module run only in slow clock domain
detection.clock := slow.clock
detection.reset := slow.reset
......@@ -70,6 +87,7 @@ class MatanaTopModuleImp(outer: MatanaTopModule, params: MatanaParams)
detection.io.packs(i).vec_hpc := RegNext(RegNext(matanaXdirect_fast_hpc))
}
}
}
}
......
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