Commit c37bffea authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

MatanaTop: adapt to no frequency difference connection (synchrone)

parent f134d3f4
...@@ -11,7 +11,7 @@ import freechips.rocketchip.util.{Pow2ClockDivider, ShiftRegInit} ...@@ -11,7 +11,7 @@ import freechips.rocketchip.util.{Pow2ClockDivider, ShiftRegInit}
// Fix: param (x) to log2(x) // Fix: param (x) to log2(x)
// Fix: Reset is async for the slow domain // Fix: Reset is async for the slow domain
class MatanaClockDivider(log2Div: Int)(implicit p: Parameters) extends LazyModule { class MatanaClockDivider(log2Div: Int)(implicit p: Parameters) extends LazyModule {
require(log2Div > 0) require(log2Div >= 0)
val node = ClockAdapterNode( val node = ClockAdapterNode(
sourceFn = { case src => src.copy(give = src.give.map(x => x.copy(freqMHz = x.freqMHz / 2))) }, sourceFn = { case src => src.copy(give = src.give.map(x => x.copy(freqMHz = x.freqMHz / 2))) },
......
...@@ -26,10 +26,9 @@ class MatanaTopModule(params: MatanaParams, beatBytes: Int)(implicit p: Paramete ...@@ -26,10 +26,9 @@ class MatanaTopModule(params: MatanaParams, beatBytes: Int)(implicit p: Paramete
val matana_slow_domain = LazyModule(new ClockSinkDomain(take = None)) val matana_slow_domain = LazyModule(new ClockSinkDomain(take = None))
matana_slow_domain.clockNode := clockdiv.node matana_slow_domain.clockNode := clockdiv.node
// TileLink and Interrupt crossing to slow clock domain // TileLink and Interrupt nodes, (optional) crossing to slow clock domain
// Was RationalCrossing(SlowToFast), dont know if it is this element that cause Linux Kernel Freezing val node = if (params.log2ClockDiv == 0) matana_slow_detection.node else TLInwardCrossingHelper("matanaXbus", matana_slow_domain, matana_slow_detection.node)(AsynchronousCrossing())
val node = TLInwardCrossingHelper("matanaXbus", matana_slow_domain, matana_slow_detection.node)(AsynchronousCrossing()) val intnode = if (params.log2ClockDiv == 0) matana_slow_detection.intnode else IntOutwardCrossingHelper("matanaXint", matana_slow_domain, matana_slow_detection.intnode)(AsynchronousCrossing())
val intnode = IntOutwardCrossingHelper("matanaXint", matana_slow_domain, matana_slow_detection.intnode)(AsynchronousCrossing())
} }
@chiselName @chiselName
...@@ -40,34 +39,53 @@ class MatanaTopModuleImp(outer: MatanaTopModule, params: MatanaParams) ...@@ -40,34 +39,53 @@ class MatanaTopModuleImp(outer: MatanaTopModule, params: MatanaParams)
val tiles = Vec(params.nHarts, Flipped(new MatanaCoreIO)) val tiles = Vec(params.nHarts, Flipped(new MatanaCoreIO))
}) })
val slow = outer.matana_slow_domain.module
val detection = outer.matana_slow_detection.module val detection = outer.matana_slow_detection.module
// Detection module run only in slow clock domain if (params.log2ClockDiv == 0) {
detection.clock := slow.clock // Without frequency difference
detection.reset := slow.reset io.tiles.zipWithIndex.map { case (tile, i) =>
// Call MatanaSync but is only for formatting
// Send Core(Tile)s information to detection module via Sequential to Parallel logic detection.io.packs(i).vec_inst_data := RegNext(MatanaSync.seq2par(1, tile.inst_data))
println(s"MatanaParams: nHarts: ${params.nHarts}; tiles: ${io.tiles}") detection.io.packs(i).vec_inst_valid := RegNext(MatanaSync.seq2par(1, tile.inst_valid))
io.tiles.zipWithIndex.map { case (tile, i) => detection.io.packs(i).one_pc_data := RegNext(tile.pc_data)
val matanaXdirect_fast_inst_data = MatanaSync.seq2par(params.clockDiv, tile.inst_data) detection.io.packs(i).one_pc_valid := RegNext(tile.pc_valid)
val matanaXdirect_fast_inst_valid = MatanaSync.seq2par(params.clockDiv, tile.inst_valid) detection.io.packs(i).one_dmemaddr_data := RegNext(tile.dmemaddr_data)
val (matanaXdirect_fast_pc_data, matanaXdirect_fast_pc_valid) = MatanaSync.seq2one(params.clockDiv, tile.pc_data, tile.pc_valid) detection.io.packs(i).one_dmemaddr_valid := RegNext(tile.dmemaddr_valid)
val (matanaXdirect_fast_dmemaddr_data, matanaXdirect_fast_dmemaddr_valid) = MatanaSync.seq2one(params.clockDiv, tile.dmemaddr_data, tile.dmemaddr_valid) detection.io.packs(i).one_dmempaddr_data := RegNext(tile.dmempaddr_data)
val (matanaXdirect_fast_dmempaddr_data, matanaXdirect_fast_dmempaddr_valid) = MatanaSync.seq2one(params.clockDiv, tile.dmempaddr_data, tile.dmempaddr_valid) detection.io.packs(i).one_dmempaddr_valid := RegNext(tile.dmempaddr_valid)
val matanaXdirect_fast_hpc = MatanaSync.seq2par(params.clockDiv, tile.hpc) detection.io.packs(i).vec_hpc := RegNext(MatanaSync.seq2par(1, tile.hpc))
// Registered at slow side }
// We do not need AsyncQueue that introduce higher latency and resources usages, as we are sure that receiver is always ready and sender is always valid
withClock(slow.clock) { } else {
detection.io.packs(i).vec_inst_data := RegNext(RegNext(matanaXdirect_fast_inst_data)) // With frequency difference
detection.io.packs(i).vec_inst_valid := RegNext(RegNext(matanaXdirect_fast_inst_valid)) val slow = outer.matana_slow_domain.module
detection.io.packs(i).one_pc_data := RegNext(RegNext(matanaXdirect_fast_pc_data))
detection.io.packs(i).one_pc_valid := RegNext(RegNext(matanaXdirect_fast_pc_valid)) // Detection module run only in slow clock domain
detection.io.packs(i).one_dmemaddr_data := RegNext(RegNext(matanaXdirect_fast_dmemaddr_data)) detection.clock := slow.clock
detection.io.packs(i).one_dmemaddr_valid := RegNext(RegNext(matanaXdirect_fast_dmemaddr_valid)) detection.reset := slow.reset
detection.io.packs(i).one_dmempaddr_data := RegNext(RegNext(matanaXdirect_fast_dmempaddr_data))
detection.io.packs(i).one_dmempaddr_valid := RegNext(RegNext(matanaXdirect_fast_dmempaddr_valid)) // Send Core(Tile)s information to detection module via Sequential to Parallel logic
detection.io.packs(i).vec_hpc := RegNext(RegNext(matanaXdirect_fast_hpc)) println(s"MatanaParams: nHarts: ${params.nHarts}; tiles: ${io.tiles}")
io.tiles.zipWithIndex.map { case (tile, i) =>
val matanaXdirect_fast_inst_data = MatanaSync.seq2par(params.clockDiv, tile.inst_data)
val matanaXdirect_fast_inst_valid = MatanaSync.seq2par(params.clockDiv, tile.inst_valid)
val (matanaXdirect_fast_pc_data, matanaXdirect_fast_pc_valid) = MatanaSync.seq2one(params.clockDiv, tile.pc_data, tile.pc_valid)
val (matanaXdirect_fast_dmemaddr_data, matanaXdirect_fast_dmemaddr_valid) = MatanaSync.seq2one(params.clockDiv, tile.dmemaddr_data, tile.dmemaddr_valid)
val (matanaXdirect_fast_dmempaddr_data, matanaXdirect_fast_dmempaddr_valid) = MatanaSync.seq2one(params.clockDiv, tile.dmempaddr_data, tile.dmempaddr_valid)
val matanaXdirect_fast_hpc = MatanaSync.seq2par(params.clockDiv, tile.hpc)
// Registered at slow side
// We do not need AsyncQueue that introduce higher latency and resources usages, as we are sure that receiver is always ready and sender is always valid
withClock(slow.clock) {
detection.io.packs(i).vec_inst_data := RegNext(RegNext(matanaXdirect_fast_inst_data))
detection.io.packs(i).vec_inst_valid := RegNext(RegNext(matanaXdirect_fast_inst_valid))
detection.io.packs(i).one_pc_data := RegNext(RegNext(matanaXdirect_fast_pc_data))
detection.io.packs(i).one_pc_valid := RegNext(RegNext(matanaXdirect_fast_pc_valid))
detection.io.packs(i).one_dmemaddr_data := RegNext(RegNext(matanaXdirect_fast_dmemaddr_data))
detection.io.packs(i).one_dmemaddr_valid := RegNext(RegNext(matanaXdirect_fast_dmemaddr_valid))
detection.io.packs(i).one_dmempaddr_data := RegNext(RegNext(matanaXdirect_fast_dmempaddr_data))
detection.io.packs(i).one_dmempaddr_valid := RegNext(RegNext(matanaXdirect_fast_dmempaddr_valid))
detection.io.packs(i).vec_hpc := RegNext(RegNext(matanaXdirect_fast_hpc))
}
} }
} }
} }
......
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