Commit b252a881 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

README: reorganize and adjust ethoc related description

parent 65c83298
......@@ -50,7 +50,6 @@ git apply ../matana/chipyard/generators/sifive-cache/sifive-cache.patch
* Can be disable by removing `define DDR3` in `BoardTop.v` and `ipcore/clkwiz_200.v`
* `ml605.ucf`
* If use DDR3 (default): add `ml605_ddr3.ucf` content at the end of `ml605.ucf`
* If use Ethernet: add `ml605_ethoc.ucf` content at the end of `ml605.ucf`
* Add those files to a Xilinx ISE project
* In Synthesize Properties, set `-keep_hierarchy=YES` (to avoid xilinx synthesis tools error)
......@@ -70,8 +69,15 @@ Then regenerate Verilog by running `make verilog` in `Chipyard/sims/verilator`.
2. Board:
- In `matana/board/BoardTop.v`, modify `localparam C_S_AXI_DATA_WIDTH = 64;` to 32.
- You can also uncomment `define ETHOC` and `define ETHOC_MASTER_AXI4_FULL` to use Ethernet (OpenCores), as EthOC only has 32-bit support.
- The problem of Ethernet 64-bit : the AXI4 adapter of Chipyard will send 2x32-bit request, where one of the 32-bit requests (even if write strobe = 0) might be outside of what Ethernet (OpenCores) can handle. It should not be that hard to fix, but is not done.
3. Ethernet (OpenCores), works only on 32 bit for now:
- For bitstream generation:
- Uncomment `define ETHOC` and `define ETHOC_MASTER_AXI4_FULL` in `BoardTop.v`
- Add `board/ml605_ethoc.ucf` content at the end of `ml605.ucf`
- For Linux configuration:
- Verify that the device tree generated by Chipyard contains its MAC address
- Set `CONFIG_ETHOC=y` in Linux, and other network related functionalities
- The problem of Ethernet 64-bit : the AXI4 adapter of Chipyard will send 2x32-bit request, where one of the 32-bit requests (even if write strobe = 0) might be outside of what Ethernet (OpenCores) can handle. It should not be that hard to fix (either on `TLToAXI()`, or a small filter before ethoc's AXI input), but is not done.
# Modify Matana
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