@@ -87,7 +87,7 @@ Then regenerate Verilog by running `make verilog` in `Chipyard/sims/verilator`.
-`RocketDecode.scala`: some definitions in Rocket core that can help instruction decode.
-`AnalyzeInst.scala`: helper class that contains analysis of a single instruction.
-`RegmapUtil.scala`: helper class that contains generation of regmap information based on registers.
-`DetectExample.scala`: example class that contains the basic structure of a detection logic.
-`DetectExample.scala`: example class that contains the basic structure of a detection logic. If you want to add a new detection logic, you can refer to this class and where it is used.
-`DetectPattern*.scala`: detection logics.
-`subsystem/`: files unrelated to Matana module itself, but are used to improve/modify the original Chipyard.
