Commit ab0288cd authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

Prime: add a addr based same pattern using physical address

parent 70690250
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
index c6d86ce5f..d71e89341 100644
index c6d86ce5f..b71537cb9 100644
--- a/src/main/scala/rocket/RocketCore.scala
+++ b/src/main/scala/rocket/RocketCore.scala
@@ -846,6 +846,23 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
@@ -846,6 +846,26 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
io.rocc.cmd.bits.rs1 := wb_reg_wdata
io.rocc.cmd.bits.rs2 := wb_reg_rs2
......@@ -15,6 +15,9 @@ index c6d86ce5f..d71e89341 100644
+ // dmem access is at ex stage
+ io.matana.dmemaddr_data := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) // copy from io.dmem.req.bits.addr
+ io.matana.dmemaddr_valid := ex_reg_valid && ex_ctrl.mem
+ // dmem physical addr s2_paddr is at wb stage (cf s2_xcpt)
+ io.matana.dmempaddr_data := io.dmem.s2_paddr
+ io.matana.dmempaddr_valid := wb_reg_valid && wb_ctrl.mem
+ // performance counters
+ io.matana.hpc.dcache_miss := io.dmem.perf.acquire
+ io.matana.hpc.dcache_blocked := id_ctrl.mem && dcache_blocked
......
......@@ -12,6 +12,9 @@ class MatanaCoreIO extends Bundle {
val pc_valid = Output(Bool())
val dmemaddr_data = Output(UInt(40.W)) // used by DCacheMetadataReq
val dmemaddr_valid = Output(Bool())
val dmempaddr_data = Output(UInt(32.W)) // In config (1MedCore + 64bit), paddrBits = 32
val dmempaddr_valid = Output(Bool())
val hpc = Output(new MatanaCoreHpcIO())
}
......
......@@ -37,6 +37,8 @@ case class MatanaParams(
// TODO: compute the real value of vaddrBitsExtended, useful for CoreIO too (refer to rocket-chip.tile.BaseTile)
private val vaddrBitsExtended : Int = if(XLen == 32) 32 else 40
val addrWidth = vaddrBitsExtended
val paddrWidth : Int = 32
}
case object MatanaKey extends Field[Option[MatanaParams]](None)
......
......@@ -16,6 +16,8 @@ class DetectPatternPrimeIn()(implicit val mp: MatanaParams) extends Bundle {
val isMonitoring = Bool()
val dmemaddr_valid = Bool()
val dmemaddr_data = UInt(mp.addrWidth.W)
val dmempaddr_valid = Bool()
val dmempaddr_data = UInt(mp.paddrWidth.W)
val pack_has_valid = Bool()
val pack_has_loadword = Bool()
}
......@@ -108,6 +110,65 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
atk_prime_2 := (count2 === countThresh2.U) && in.isMonitoring && in.dmemaddr_valid
// Attack pattern (physical address)
// Description: Multiples access to DCache, each time in same set with differents tag
// 1) diff tag same set c+2, diff tag diff set c+1, same tag same set c-2, same tag diff set c-1 (thresh 8)
// 2) diff tag same set c+2, diff tag diff set c+1, same tag same set c-4, same tag diff set c-2 (thresh 8)
val dmemptag = Wire(UInt((mp.paddrWidth - params.tagAddrLSB).W))
dmemptag := in.dmempaddr_data(mp.paddrWidth - 1, params.tagAddrLSB)
val dmempset = Wire(UInt((params.tagAddrLSB - params.setAddrLSB).W))
dmempset := in.dmempaddr_data(params.tagAddrLSB - 1, params.setAddrLSB)
val saved_dmemptag = RegInit(VecInit(Seq.fill(params.savedDMemTagNum)(0.U((mp.addrWidth - params.tagAddrLSB).W)))).suggestName("saved_dmemptag")
val saved_dmempset = RegInit(VecInit(Seq.fill(params.savedDMemSetNum)(0.U((params.tagAddrLSB - params.setAddrLSB).W)))).suggestName("saved_dmempset")
val countp1 = RegInit(0.U(log2Ceil(countThresh1 + 1).W)).suggestName("dpprime_countp1")
val countp2 = RegInit(0.U(log2Ceil(countThresh2 + 1).W)).suggestName("dpprime_countp2")
// Update saved_dmem* array in FIFO way
when (in.dmempaddr_valid && in.isMonitoring) {
when (saved_dmemptag.map(_ =/= dmemptag).reduce(_&&_)) { // new tag
when (saved_dmempset.map(_ =/= dmempset).reduce(_&&_)) { // new set
// Update saved_dmempset, newer at 0
saved_dmempset.foldLeft(dmempset) { (data, last) =>
last := data
last
}
countp1 := Mux(countp1 <= countThresh1.U - 1.U, countp1 + 1.U, countThresh1.U)
countp2 := Mux(countp2 <= countThresh2.U - 1.U, countp2 + 1.U, countThresh2.U)
}.otherwise { // old set
countp1 := Mux(countp1 <= countThresh1.U - 2.U, countp1 + 2.U, countThresh1.U)
countp2 := Mux(countp2 <= countThresh2.U - 2.U, countp2 + 2.U, countThresh2.U)
}
// Update saved_dmemptag, newer at 0
saved_dmemptag.foldLeft(dmemptag) { (data, last) =>
last := data
last
}
}.otherwise { // old tag
when (saved_dmempset.map(_ =/= dmemptag).reduce(_&&_)) { // new set
// Update saved_dmempset, newer at 0
saved_dmempset.foldLeft(dmempset) { (data, last) =>
last := data
last
}
countp1 := Mux(countp1 >= 1.U, countp1 - 1.U, 0.U)
countp2 := Mux(countp2 >= 2.U, countp2 - 2.U, 0.U)
}.otherwise { // old set
countp1 := Mux(countp1 >= 2.U, countp1 - 2.U, 0.U)
countp2 := Mux(countp2 >= 4.U, countp2 - 4.U, 0.U)
}
}
}
// only count atk during monitoring, and when an dmempaddr is present (prevent counting during wait)
val atk_prime_phy_1 = RegInit(false.B)
atk_prime_phy_1 := (countp1 === countThresh1.U) && in.isMonitoring && in.dmempaddr_valid
val atk_prime_phy_2 = RegInit(false.B)
atk_prime_phy_2 := (countp2 === countThresh2.U) && in.isMonitoring && in.dmempaddr_valid
// Attack Pattern (instruction-based)
// Description: all valid pack contains an word size load. For -O0 there is store with load, we suppose if store to the same addr, the next load can be conclude in the same slow cycle.
// 1) valid load c+1, valid not load c-2 (thresh 16)
......@@ -161,6 +222,8 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
RegmapUtil.countEvent(atk_primeinst_1, in.resetCounters, offset + 0x10, "AtkPrimeInst1") ++
RegmapUtil.countEventMax(atk_prime_1, in.resetCounters, atk_prime_mix1_dec, offset + 0x20, "AtkPrimeMix1") ++
RegmapUtil.countEventMax(atk_prime_1, in.resetCounters, atk_prime_mix2_dec, offset + 0x30, "AtkPrimeMix2") ++
RegmapUtil.countEvent(atk_prime_phy_1, in.resetCounters, offset + 0x40, "AtkPrimePhy1") ++
RegmapUtil.countEvent(atk_prime_phy_2, in.resetCounters, offset + 0x44, "AtkPrimePhy2") ++
Nil
}
......
......@@ -36,6 +36,8 @@ class MatanaDetectionPerCoreIO()(implicit val mp: MatanaParams) extends Bundle {
val one_pc_valid = Input(Bool())
val one_dmemaddr_data = Input(UInt(mp.addrWidth.W))
val one_dmemaddr_valid = Input(Bool())
val one_dmempaddr_data = Input(UInt(mp.paddrWidth.W))
val one_dmempaddr_valid = Input(Bool())
// Performance counters
val vec_hpc = Input(Vec(mp.clockDiv, new MatanaCoreHpcIO()))
}
......@@ -133,6 +135,8 @@ class MatanaSlowDetectionImp(outer: MatanaSlowDetection, params: MatanaParams)
detectPatternPrime.in.isMonitoring := isMonitoring
detectPatternPrime.in.dmemaddr_valid := pack0.one_dmemaddr_valid
detectPatternPrime.in.dmemaddr_data := pack0.one_dmemaddr_data
detectPatternPrime.in.dmempaddr_valid := pack0.one_dmempaddr_valid
detectPatternPrime.in.dmempaddr_data := pack0.one_dmempaddr_data
detectPatternPrime.in.pack_has_valid := pack_has_valid
detectPatternPrime.in.pack_has_loadword := pack_has_loadword
......
......@@ -54,6 +54,7 @@ class MatanaTopModuleImp(outer: MatanaTopModule, params: MatanaParams)
val matanaXdirect_fast_inst_valid = MatanaSync.seq2par(params.clockDiv, tile.inst_valid)
val (matanaXdirect_fast_pc_data, matanaXdirect_fast_pc_valid) = MatanaSync.seq2one(params.clockDiv, tile.pc_data, tile.pc_valid)
val (matanaXdirect_fast_dmemaddr_data, matanaXdirect_fast_dmemaddr_valid) = MatanaSync.seq2one(params.clockDiv, tile.dmemaddr_data, tile.dmemaddr_valid)
val (matanaXdirect_fast_dmempaddr_data, matanaXdirect_fast_dmempaddr_valid) = MatanaSync.seq2one(params.clockDiv, tile.dmempaddr_data, tile.dmempaddr_valid)
val matanaXdirect_fast_hpc = MatanaSync.seq2par(params.clockDiv, tile.hpc)
// Registered at slow side
// We do not need AsyncQueue that introduce higher latency and resources usages, as we are sure that receiver is always ready and sender is always valid
......@@ -64,6 +65,8 @@ class MatanaTopModuleImp(outer: MatanaTopModule, params: MatanaParams)
detection.io.packs(i).one_pc_valid := RegNext(RegNext(matanaXdirect_fast_pc_valid))
detection.io.packs(i).one_dmemaddr_data := RegNext(RegNext(matanaXdirect_fast_dmemaddr_data))
detection.io.packs(i).one_dmemaddr_valid := RegNext(RegNext(matanaXdirect_fast_dmemaddr_valid))
detection.io.packs(i).one_dmempaddr_data := RegNext(RegNext(matanaXdirect_fast_dmempaddr_data))
detection.io.packs(i).one_dmempaddr_valid := RegNext(RegNext(matanaXdirect_fast_dmempaddr_valid))
detection.io.packs(i).vec_hpc := RegNext(RegNext(matanaXdirect_fast_hpc))
}
}
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment