Commit 9a3a53ba authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

README: add project structure description

parent b2cbb69a
......@@ -2,8 +2,9 @@
[Chipyard 1.3.0](https://github.com/ucb-bar/chipyard/tree/1.3.0)
Some of adaptation to 1.5.0 have been proposed to branch `dev-chipyard1.5` but is not finished.
Some of adaptation to 1.5.0 has been proposed to branch `dev-chipyard1.5` but is not finished.
# Usage
## Setup
......@@ -15,7 +16,7 @@ Then apply patches to include MATANA into Chipyard.
cd <path/to/Chipyard>
git submodule add https://gitlab.laas.fr/matana/matana-chipyard generators/matana
# Apply patch that connect MATANA to Chipyard + Rocket-Chip + ...
# Apply patch that connects MATANA to Chipyard + Rocket-Chip + ...
git apply generators/matana/chipyard/chipyard.patch
cd generators/rocket-chip
git apply ../matana/chipyard/generators/rocket-chip/rocket-chip.patch
......@@ -61,12 +62,40 @@ git apply ../matana/chipyard/generators/sifive-cache/sifive-cache.patch
## Switch between 64bit and 32bit
To use 32bit system:
To use 32-bit system:
1. Cores:
- (Rocket core) In `matana/chipyard/generators/chipyard/MatanaConfig.scala`, uncomment `new freechips.rocketchip.subsystem.WithRV32 ++`.
Then regenerate verilog by running `make verilog` in `Chipyard/sims/verilator`.
Then regenerate Verilog by running `make verilog` in `Chipyard/sims/verilator`.
2. Board:
- In `matana/board/BoardTop.v`, modify `localparam C_S_AXI_DATA_WIDTH = 64;` to 32.
- You can also uncomment `define ETHOC` and `define ETHOC_MASTER_AXI4_FULL` to use Ethernet (OpenCores), as EthOC only has 32-bit support.
- The problem of Ethernet 64-bit : the AXI4 adapter of Chipyard will send 2x32-bit request, where one of the 32-bit requests (even if write strobe = 0) might be outside of what Ethernet (OpenCores) can handle. It should not be that hard to fix, but is not done.
# Project structure
- `src/main/scala/`: main reposiroty of Matana hardware Detection Module.
- `Configs.scala`: configure Matana module. Such as the clock division rate, the activated detection logic.
- `MatanaTop.scala`: top file that declares Matana connections, this part of hardware will run at high frequency domain.
- `MatanaSync.scala`: helper class that contains dedicated connection declarations for monitored signals and a fixed ClockDivider.
- `MatanaSlowDetection.scala`: top file of the detections logics, all content in this file work in slow clock domain, it is the part that should be totally placed in a reconfigurable fabric such as a FPGA in the final system.
- `RocketDecode.scala`: some definitions in Rocket core that can help instruction decode.
- `AnalyzeInst.scala`: helper class that contains analysis of a single instruction.
- `RegmapUtil.scala`: helper class that contains generation of regmap information based on registers.
- `DetectExample.scala`: example class that contains the basic structure of a detection logic.
- `DetectPattern*.scala`: detection logics.
- `subsystem/`: files unrelated to Matana module itself, but are used to improve/modify the original Chipyard.
- `board/`: Verilog files that helps to work in ML605 board.
- `bootrom/`: Bootrom program that will be included in Chipyard BootROM. Compared to Chipyard's version, it did not use wfi, and accept external interruption. If modified, you need to run `make` in this directory.
- `chipyard/`: contains patches made on the original Chipyard project.
- `target/`: generated files by Chipyard build system.
- `build.sbt`: to integrate into Chipyard build system.
- `Note.md`: additional notes, including some problems encountered and their solution (if any).
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