Commit 93f48c00 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

trait top: move rehad trait back to rehad package, add support for no rehad. gen Verilog ok

parent 890f3ba4
......@@ -41,19 +41,19 @@ index 0000000..90e80dd
@@ -0,0 +1 @@
+../../../../rehad/chipyard/generators/chipyard/src/main/scala/ImplemTop.scala
\ No newline at end of file
diff --git a/generators/chipyard/src/main/scala/Rehad.scala b/generators/chipyard/src/main/scala/Rehad.scala
new file mode 120000
index 0000000..f557b44
--- /dev/null
+++ b/generators/chipyard/src/main/scala/Rehad.scala
@@ -0,0 +1 @@
+../../../../rehad/chipyard/generators/chipyard/src/main/scala/Rehad.scala
\ No newline at end of file
diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index 99c3147..68b96ad 100644
index 99c3147..abbfc1e 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -89,6 +89,7 @@ trait HasChipyardTilesModuleImp extends HasTilesModuleImp
@@ -25,6 +25,7 @@ import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams}
import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
import testchipip.{DromajoHelper}
+import rehad.{CanHavePeripheryRehad, CanHavePeripheryRehadImp}
trait HasChipyardTiles extends HasTiles
with CanHavePeripheryPLIC
@@ -89,6 +90,7 @@ trait HasChipyardTilesModuleImp extends HasTilesModuleImp
class Subsystem(implicit p: Parameters) extends BaseSubsystem
with HasChipyardTiles
......@@ -61,7 +61,7 @@ index 99c3147..68b96ad 100644
{
override lazy val module = new SubsystemModuleImp(this)
@@ -98,6 +99,7 @@ class Subsystem(implicit p: Parameters) extends BaseSubsystem
@@ -98,6 +100,7 @@ class Subsystem(implicit p: Parameters) extends BaseSubsystem
class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasResetVectorWire
with HasChipyardTilesModuleImp
......@@ -69,12 +69,18 @@ index 99c3147..68b96ad 100644
{
tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
wire.hartid := i.U
@@ -110,4 +112,6 @@ class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModule
@@ -110,4 +113,12 @@ class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModule
// Generate C header with relevant information for Dromajo
// This is included in the `dromajo_params.h` header file
DromajoHelper.addArtefacts
+
+ _outer.rehad.get.module.io.tiles <> tile_rehads
+ // Optionally connect tiles to rehad module
+ _outer.rehad match {
+ case Some(rehad) => {
+ rehad.module.io.tiles <> tile_rehads
+ }
+ case None => None
+ }
}
diff --git a/generators/chipyard/src/main/scala/config/RehadConfigs.scala b/generators/chipyard/src/main/scala/config/RehadConfigs.scala
new file mode 120000
......
package chipyard
import chisel3._
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.subsystem.BaseSubsystem
import rehad._
trait CanHavePeripheryRehad { this: BaseSubsystem =>
private val portName = "rehad"
val rehad = p(RehadKey) match {
case Some(params) => {
val rehad = LazyModule(new RehadTopModule(params, pbus.beatBytes)(p))
pbus.toVariableWidthSlaveNode(Some(portName)) { rehad.node }
ibus.fromSync := rehad.intnode
rehad.clockdiv.node := pbus.clockNode
Some(rehad)
}
case None => None
}
}
trait CanHavePeripheryRehadImp extends LazyModuleImp {
val outer: CanHavePeripheryRehad
}
......@@ -10,6 +10,7 @@ import freechips.rocketchip.prci.ClockSinkDomain
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction}
import freechips.rocketchip.rocket.{IntCtrlSigs, CSR, CSRs}
import freechips.rocketchip.rocket.constants.MemoryOpConstants
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.tile.RehadCoreIO
import freechips.rocketchip.tilelink.{TLRegisterNode,TLInwardCrossingHelper}
import freechips.rocketchip.util.SlowToFast
......@@ -226,3 +227,22 @@ class RehadTopModule(params: RehadParams, beatBytes: Int)(implicit p: Parameters
val node = TLInwardCrossingHelper("rehadXnode", rehad_slow_domain, rehad_slow_detection.node)(RationalCrossing(SlowToFast))
val intnode = IntOutwardCrossingHelper("rehadXint", rehad_slow_domain, rehad_slow_detection.intnode)(RationalCrossing(SlowToFast))
}
trait CanHavePeripheryRehad { this: BaseSubsystem =>
private val portName = "rehad"
val rehad = p(RehadKey) match {
case Some(params) => {
val rehad = LazyModule(new RehadTopModule(params, pbus.beatBytes)(p))
pbus.toVariableWidthSlaveNode(Some(portName)) { rehad.node }
ibus.fromSync := rehad.intnode
rehad.clockdiv.node := pbus.clockNode
Some(rehad)
}
case None => None
}
}
trait CanHavePeripheryRehadImp extends LazyModuleImp {
val outer: CanHavePeripheryRehad
}
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