Commit 784261e7 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

DetectPrime: add isMonitoring to internal state change condition, modify some not very good pattern

parent df6b33e5
......@@ -79,7 +79,7 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
val count8 = RegInit(0.U(log2Ceil(countThresh8 + 1).W)).suggestName("dpprime_count8")
// Update saved_dmem* array in FIFO way
when (in.dmemaddr_valid) {
when (in.dmemaddr_valid && in.isMonitoring) {
when (saved_dmemtag.map(_ =/= dmemtag).reduce(_&&_)) { // new tag
when (saved_dmemset.map(_ =/= dmemset).reduce(_&&_)) { // new set
// Update saved_dmemset, newer at 0
......@@ -160,12 +160,12 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
// Attack Pattern
// Description: all valid pack contains an word size load
// 1) valid load c+1, valid not load c-1 (thresh 32)
// 2) valid load c+1, valid not load c-2 (thresh 8) (maybe only apply to high clkDiv, as for -O0 there is store with load. we suppose if store to the same addr, the next load can be conclude in the same slow cycle)
// 2) valid load c+1, valid not load c-2 (thresh 32) (maybe only apply to high clkDiv, as for -O0 there is store with load. we suppose if store to the same addr, the next load can be conclude in the same slow cycle)
// 3) valid load c+1, valid not load c-2 (thresh 16)
// 4) valid load c+1, valid not load c-1 (thresh 16)
// 4) valid load c+1, valid not load c-4 (thresh 16)
val countInstThresh1 = 32
val countInstThresh2 = 8
val countInstThresh2 = 32
val countInstThresh3 = 16
val countInstThresh4 = 16
val countinst1 = RegInit(0.U(log2Ceil(countInstThresh1 + 1).W)).suggestName("dpprime_countinst1")
......@@ -173,7 +173,7 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
val countinst3 = RegInit(0.U(log2Ceil(countInstThresh3 + 1).W)).suggestName("dpprime_countinst3")
val countinst4 = RegInit(0.U(log2Ceil(countInstThresh4 + 1).W)).suggestName("dpprime_countinst4")
when (in.pack_has_valid) {
when (in.pack_has_valid && in.isMonitoring) {
when (in.pack_has_loadword) {
countinst1 := Mux(countinst1 <= countInstThresh1.U - 1.U, countinst1 + 1.U, countInstThresh1.U)
countinst2 := Mux(countinst2 <= countInstThresh2.U - 1.U, countinst2 + 1.U, countInstThresh2.U)
......@@ -183,7 +183,7 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
countinst1 := Mux(countinst1 >= 1.U, countinst1 - 1.U, 0.U)
countinst2 := Mux(countinst2 >= 2.U, countinst2 - 2.U, 0.U)
countinst3 := Mux(countinst3 >= 2.U, countinst3 - 2.U, 0.U)
countinst4 := Mux(countinst4 >= 1.U, countinst4 - 1.U, 0.U)
countinst4 := Mux(countinst4 >= 4.U, countinst4 - 4.U, 0.U)
}
}
......@@ -200,9 +200,9 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
// Attack Pattern
// Description: Mix pattern
// 1) count4, but decrement the counter by 1 if count_pack_valid reach thresh (0x800)
// 1) count4, but decrement the counter by 1 if count_pack_valid reach thresh (0x200=512)
// => TODO: perhaps adjust using dmemaddr / slow cycle count
// 2) count4+countinst4: if 2 atk are recognized in 4 slow cycles
// 2) count4+countinst4: if 2 atk are recognized in 8 slow cycles
// 3) count4+countinst4: (similar to mix2 but use 1 counter for both count4 and countinst4)
// count4 max && countinst4 max: c+8
// count4 max || countinst4 max: c+4
......@@ -216,13 +216,13 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
// (max 12, thresh 9)
// 5) count4+countinst4: (only take when c4/ci4=max or c4/ci4=0, if thresh then 0 to prevent cmix remains max) TODO?
val countPackValidThresh = 0x800L // 2048
val countPackValidThresh = 0x200L
val count_pack_valid = RegInit(0.U(mp.counterWidth.W)).suggestName("dpprime_count_pack_valid")
val count_pack_valid_dec = RegInit(false.B).suggestName("dpprime_count_pack_valid_dec")
when (in.resetCounters) {
count_pack_valid := 0.U
count_pack_valid_dec := false.B
}.otherwise {
}.elsewhen (in.isMonitoring) {
when (count_pack_valid =/= countPackValidThresh.U) { // count < thresh
count_pack_valid := count_pack_valid + in.pack_has_valid
count_pack_valid_dec := false.B
......@@ -235,15 +235,15 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
val atk_primemix_1 = Wire(Bool())
atk_primemix_1 := Mux(count_pack_valid_dec, !atk_prime_4, atk_prime_4) && in.isMonitoring // if dec=true, dec1 if atk0, dec0 if atk1; if dec=false, inc1 if atk1, inc0 if atk0.
val countMix2Thresh = 4
val countMix2Thresh = 8
val countmix2_1 = RegInit(0.U(log2Ceil(countMix2Thresh + 1).W)).suggestName("dpprime_countmix2_1")
val countmix2_2 = RegInit(0.U(log2Ceil(countMix2Thresh + 1).W)).suggestName("dpprime_countmix2_2")
when (in.dmemaddr_valid) { // modify counter only when valid
when (in.dmemaddr_valid && in.isMonitoring) { // modify counter only when valid
countmix2_1 := Mux(count4 === countThresh4.U,
countMix2Thresh.U, // if count4 max, set countmix2_1 to max
Mux(countmix2_1 <= 1.U, 0.U, countmix2_1 - 1.U)) // else decrement
}
when (in.pack_has_valid) { // modify counter only when valid
when (in.pack_has_valid && in.isMonitoring) { // modify counter only when valid
countmix2_2 := Mux(countinst4 === countInstThresh4.U,
countMix2Thresh.U, // if countinst4 max, set countmix2_2 to max
Mux(countmix2_2 <= 1.U, 0.U, countmix2_2 - 1.U)) // else decrement
......@@ -262,21 +262,23 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
countmix3state := Cat((count4 === countThresh4.U) && in.dmemaddr_valid,
(countinst4 === countInstThresh4.U) && in.pack_has_valid)
when (countmix3state.andR) {
countmix3 := Mux(countmix3 <= countMix3Max.U - 8.U, countmix3 + 8.U, countMix3Max.U)
countmix4 := Mux(countmix4 <= countMix4Max.U - 12.U, countmix4 + 12.U, countMix4Max.U)
}.elsewhen (countmix3state(0) === true.B) {
countmix3 := Mux(countmix3 <= countMix3Max.U - 4.U, countmix3 + 4.U, countMix3Max.U)
countmix4 := Mux(countmix4 <= countMix4Max.U - 8.U, countmix4 + 8.U, countMix4Max.U)
}.elsewhen (countmix3state(1) === true.B) {
countmix3 := Mux(countmix3 <= countMix3Max.U - 4.U, countmix3 + 4.U, countMix3Max.U)
countmix4 := Mux(countmix4 <= countMix4Max.U - 4.U, countmix4 + 4.U, countMix4Max.U)
}.elsewhen (in.dmemaddr_valid || in.pack_has_valid) { // has valid input, should decrement
countmix3 := Mux(countmix3 >= 1.U, countmix3 - 1.U, 0.U)
countmix4 := Mux(countmix4 >= 1.U, countmix4 - 1.U, 0.U)
}.otherwise { // no valid package, remains old value
countmix3 := countmix3
countmix4 := countmix4
when (in.resetCounters) {
countmix3 := 0.U
countmix4 := 0.U
}.elsewhen (in.isMonitoring) {
when (countmix3state.andR) {
countmix3 := Mux(countmix3 <= countMix3Max.U - 8.U, countmix3 + 8.U, countMix3Max.U)
countmix4 := Mux(countmix4 <= countMix4Max.U - 12.U, countmix4 + 12.U, countMix4Max.U)
}.elsewhen (countmix3state(0) === true.B) {
countmix3 := Mux(countmix3 <= countMix3Max.U - 4.U, countmix3 + 4.U, countMix3Max.U)
countmix4 := Mux(countmix4 <= countMix4Max.U - 8.U, countmix4 + 8.U, countMix4Max.U)
}.elsewhen (countmix3state(1) === true.B) {
countmix3 := Mux(countmix3 <= countMix3Max.U - 4.U, countmix3 + 4.U, countMix3Max.U)
countmix4 := Mux(countmix4 <= countMix4Max.U - 4.U, countmix4 + 4.U, countMix4Max.U)
}.elsewhen (in.dmemaddr_valid || in.pack_has_valid) { // has valid input, should decrement
countmix3 := Mux(countmix3 >= 1.U, countmix3 - 1.U, 0.U)
countmix4 := Mux(countmix4 >= 1.U, countmix4 - 1.U, 0.U)
} // otherwise no valid package, remains old value
}
val atk_primemix_3 = Wire(Bool())
......
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