Commit 6e34cc77 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

DetectCacheEvent: add event counters with decrement

parent 3ce18a13
......@@ -10,6 +10,7 @@ case class DetectPatternCacheEventParams(
class DetectPatternCacheEventIn()(implicit val mp: MatanaParams) extends Bundle {
val resetCounters = Bool()
val isMonitoring = Bool()
val pack_has_valid = Bool()
val vec_hpc = Vec(mp.clockDiv, new MatanaCoreHpcIO())
}
......@@ -21,17 +22,50 @@ class DetectPatternCacheEvent()(implicit mp: MatanaParams) {
class DetectPatternCacheEventInternal(params: DetectPatternCacheEventParams)(implicit mp: MatanaParams) extends DetectPatternCacheEvent {
// Attack pattern
// Description: a high rate of cache miss / instruction
// Description: a high rate of Data cache miss / instruction
// -) Count pack_has_dcache_miss event (as count the exact value is difficult)
// N) = atk_dcache_miss, but decrement by 1 if count_pack_valid reach thresh X
val pack_has_dcache_miss = RegInit(false.B)
val pack_has_dcache_miss = RegInit(false.B).suggestName("dpdcacheevent_pack_has_dcache_miss")
pack_has_dcache_miss := in.vec_hpc.map(_.dcache_miss).reduce(_||_)
val atk_dcache_miss = RegInit(false.B)
atk_dcache_miss := pack_has_dcache_miss && in.isMonitoring
// Count pack valid for decrement counters
val count_pack_valid = RegInit(0.U(mp.counterWidth.W)).suggestName("dpdcacheevent_count_pack_valid")
when (in.resetCounters) {
count_pack_valid := 0.U
}.elsewhen (in.isMonitoring) {
count_pack_valid := count_pack_valid + in.pack_has_valid
}
val countPackValidThreshLengthMinus1_1 = 2 // Thresh = 2^(2+1) = 8 = 0x8 (0b000)
val countPackValidThreshLengthMinus1_2 = 4 // Thresh = 2^(4+1) = 32 = 0x20
val countPackValidThreshLengthMinus1_3 = 6 // Thresh = 2^(6+1) = 128 = 0x80
val countPackValidThreshLengthMinus1_4 = 8 // Thresh = 2^(8+1) = 512 = 0x200
val countPackValidThreshLengthMinus1_5 = 10 // Thresh = 2^(10+1) = 2048 = 0x800
val atk_dcache_miss_dec1 = RegInit(false.B)
atk_dcache_miss_dec1 := count_pack_valid(countPackValidThreshLengthMinus1_1, 0) === 0.U
val atk_dcache_miss_dec2 = RegInit(false.B)
atk_dcache_miss_dec2 := count_pack_valid(countPackValidThreshLengthMinus1_2, 0) === 0.U
val atk_dcache_miss_dec3 = RegInit(false.B)
atk_dcache_miss_dec3 := count_pack_valid(countPackValidThreshLengthMinus1_3, 0) === 0.U
val atk_dcache_miss_dec4 = RegInit(false.B)
atk_dcache_miss_dec4 := count_pack_valid(countPackValidThreshLengthMinus1_4, 0) === 0.U
val atk_dcache_miss_dec5 = RegInit(false.B)
atk_dcache_miss_dec5 := count_pack_valid(countPackValidThreshLengthMinus1_5, 0) === 0.U
val atk_dcache_miss1 = Wire(Bool()) // or RegInit(false.B) to reduce circuit complexity
atk_dcache_miss1 := pack_has_dcache_miss && in.isMonitoring
override def regmap(offset: Int) =
RegmapUtil.countEventThreshAlarm(atk_dcache_miss1, in.resetCounters, offset, "AtkDCacheMiss1")
RegmapUtil.countEvent(atk_dcache_miss, in.resetCounters, offset, "AtkDCacheEventMiss") ++
RegmapUtil.countEventMax(atk_dcache_miss, in.resetCounters, atk_dcache_miss_dec1, offset + 0x10, "AtkDCacheEventMiss1") ++
RegmapUtil.countEventMax(atk_dcache_miss, in.resetCounters, atk_dcache_miss_dec2, offset + 0x18, "AtkDCacheEventMiss2") ++
RegmapUtil.countEventMax(atk_dcache_miss, in.resetCounters, atk_dcache_miss_dec3, offset + 0x20, "AtkDCacheEventMiss3") ++
RegmapUtil.countEventMax(atk_dcache_miss, in.resetCounters, atk_dcache_miss_dec4, offset + 0x28, "AtkDCacheEventMiss4") ++
RegmapUtil.countEventMax(atk_dcache_miss, in.resetCounters, atk_dcache_miss_dec5, offset + 0x30, "AtkDCacheEventMiss5") ++
Nil
}
object DetectPatternCacheEvent {
......
......@@ -146,6 +146,7 @@ class MatanaSlowDetectionImp(outer: MatanaSlowDetection, params: MatanaParams)
val detectPatternCacheEvent = DetectPatternCacheEvent()
detectPatternCacheEvent.in.resetCounters := resetCounters
detectPatternCacheEvent.in.isMonitoring := isMonitoring
detectPatternCacheEvent.in.pack_has_valid := pack_has_valid
detectPatternCacheEvent.in.vec_hpc := pack0.vec_hpc
// Test PC
......
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