Commit 56af5974 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

Detect: modify some Wire to Reg, minor fix on comment

parent 403bcde4
......@@ -30,7 +30,8 @@ class DetectExampleInternal(params: DetectExampleParams)(implicit mp: MatanaPara
// The regmap for bus
override def regmap(offset: Int) =
RegmapUtil.countEventThreshAlarm(atk_example, in.resetCounters, offset, "AtkExample")
RegmapUtil.countEventThreshAlarm(atk_example, in.resetCounters, offset, "AtkExample") ++
Nil
}
object DetectExample {
......
......@@ -102,9 +102,9 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
}
// only count atk during monitoring, and when an dmemaddr is present (prevent counting during wait)
val atk_prime_1 = Wire(Bool())
val atk_prime_1 = RegInit(false.B)
atk_prime_1 := (count1 === countThresh1.U) && in.isMonitoring && in.dmemaddr_valid
val atk_prime_2 = Wire(Bool())
val atk_prime_2 = RegInit(false.B)
atk_prime_2 := (count2 === countThresh2.U) && in.isMonitoring && in.dmemaddr_valid
......@@ -124,7 +124,7 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
}
// only count atk during monitoring, and when an valid inst is present (prevent counting during wait)
val atk_primeinst_1 = Wire(Bool())
val atk_primeinst_1 = RegInit(false.B)
atk_primeinst_1 := (countinst1 === countInstThresh1.U) && in.isMonitoring && in.pack_has_valid
......@@ -148,7 +148,7 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
}
}
val atk_primemix_1 = Wire(Bool())
val atk_primemix_1 = RegInit(false.B)
atk_primemix_1 := Mux(count_pack_valid_dec, !atk_prime_1, atk_prime_1) && in.isMonitoring // if dec=true, dec1 if atk0, dec0 if atk1; if dec=false, inc1 if atk1, inc0 if atk0.
......
......@@ -44,7 +44,7 @@ class DetectPatternRopInternal(params: DetectPatternRopParams)(implicit mp: Mata
when (in.resetCounters) {
countjalr1 := 0.U
}.otherwise {
when (in.isMonitoring && in.pack_has_jump) { // evaluate counter3 when jump (include pack_has_valid)
when (in.isMonitoring && in.pack_has_jump) { // evaluate counter when jump (include pack_has_valid)
countjalr1 := Mux(in.pack_has_jalr && npack_jalr(0),
countjalr1 + 1.U,
Mux(countjalr1 >= 2.U, countjalr1 - 2.U, 0.U))
......
......@@ -35,15 +35,17 @@ class DetectPatternTimerInternal(params: DetectPatternTimerParams)(implicit mp:
val npackSize: Int = params.npackSizeInFastCycles / mp.clockDiv
val npack_timer = RegInit(0.U(npackSize.W)).suggestName("npack_timer")
val npack_timer_orR = RegInit(false.B)
when (in.pack_has_valid) {
npack_timer := Cat(npack_timer(npackSize-2, 0), in.pack_has_timer)
npack_timer_orR := npack_timer(npackSize-2, 0).orR || in.pack_has_timer
}
val atk_timer_timer = Wire(Bool())
atk_timer_timer := npack_timer.orR && in.pack_has_timer && in.isMonitoring
atk_timer_timer := npack_timer_orR && in.pack_has_timer && in.isMonitoring
val atk_timer_flush = Wire(Bool())
atk_timer_flush := npack_timer.orR && in.pack_has_flush && in.isMonitoring
atk_timer_flush := npack_timer_orR && in.pack_has_flush && in.isMonitoring
override def regmap(offset: Int) =
(if (params.withTimerTimer) RegmapUtil.countEventThreshAlarm(atk_timer_timer, in.resetCounters, offset, "AtkTimerTimer") else Nil) ++
......
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