Commit 403bcde4 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

DetectCacheEvent: add basic connection to vec hpc

parent 0cada9c0
......@@ -12,11 +12,11 @@ class MatanaCoreIO extends Bundle {
val pc_valid = Output(Bool())
val dmemaddr_data = Output(UInt(40.W)) // used by DCacheMetadataReq
val dmemaddr_valid = Output(Bool())
val hpc = new MatanaCoreHpcIO()
val hpc = Output(new MatanaCoreHpcIO())
}
class MatanaCoreHpcIO extends Bundle {
val dcache_miss = Output(Bool())
val dcache_release = Output(Bool())
val branch_mispredict = Output(Bool())
val dcache_miss = Bool()
val dcache_release = Bool()
val branch_mispredict = Bool()
}
......@@ -19,6 +19,7 @@ case class MatanaParams(
dExample: Option[DetectExampleParams] = None, //Some(DetectExampleParams()),
dPatternTimer: Option[DetectPatternTimerParams] = Some(DetectPatternTimerParams()),
dPatternPrime: Option[DetectPatternPrimeParams] = Some(DetectPatternPrimeParams()),
dPatternCacheEvent: Option[DetectPatternCacheEventParams] = Some(DetectPatternCacheEventParams()),
dPatternLibAccess: Option[DetectPatternLibAccessParams] = Some(DetectPatternLibAccessParams()),
dPatternRop: Option[DetectPatternRopParams] = Some(DetectPatternRopParams()),
counterWidth: Int = 32
......
package matana
import chisel3._
import freechips.rocketchip.regmapper.RegField
import freechips.rocketchip.tile.MatanaCoreHpcIO
case class DetectPatternCacheEventParams(
)
class DetectPatternCacheEventIn()(implicit val mp: MatanaParams) extends Bundle {
val resetCounters = Bool()
val isMonitoring = Bool()
val vec_hpc = Vec(mp.clockDiv, new MatanaCoreHpcIO())
}
class DetectPatternCacheEvent()(implicit mp: MatanaParams) {
val in = Wire(new DetectPatternCacheEventIn())
def regmap(offset: Int): Seq[(Int, Seq[RegField])] = Nil
}
class DetectPatternCacheEventInternal(params: DetectPatternCacheEventParams)(implicit mp: MatanaParams) extends DetectPatternCacheEvent {
// Attack pattern
// Description: a high rate of cache miss / instruction
val pack_has_dcache_miss = RegInit(false.B)
pack_has_dcache_miss := in.vec_hpc.map(_.dcache_miss).reduce(_||_)
val atk_dcache_miss1 = Wire(Bool()) // or RegInit(false.B) to reduce circuit complexity
atk_dcache_miss1 := pack_has_dcache_miss && in.isMonitoring
override def regmap(offset: Int) =
RegmapUtil.countEventThreshAlarm(atk_dcache_miss1, in.resetCounters, offset, "AtkDCacheMiss1")
}
object DetectPatternCacheEvent {
def apply()(implicit mp: MatanaParams) : DetectPatternCacheEvent = {
mp.dPatternCacheEvent match {
case Some(params) => new DetectPatternCacheEventInternal(params)
case None => new DetectPatternCacheEvent()
}
}
}
......@@ -143,6 +143,11 @@ class MatanaSlowDetectionImp(outer: MatanaSlowDetection, params: MatanaParams)
detectPatternRop.in.pack_has_jalr := pack_has_jalr
detectPatternRop.in.pack_has_jump := pack_has_jump
val detectPatternCacheEvent = DetectPatternCacheEvent()
detectPatternCacheEvent.in.resetCounters := resetCounters
detectPatternCacheEvent.in.isMonitoring := isMonitoring
detectPatternCacheEvent.in.vec_hpc := pack0.vec_hpc
// Test PC
val lastPC = RegInit(0.U(mp.addrWidth.W))
lastPC := Mux(pack0.one_pc_valid, pack0.one_pc_data, lastPC)
......@@ -202,6 +207,7 @@ class MatanaSlowDetectionImp(outer: MatanaSlowDetection, params: MatanaParams)
detectPatternTimer.regmap(0x200) ++
detectPatternPrime.regmap(0x300) ++
detectPatternRop.regmap(0x400) ++
detectPatternCacheEvent.regmap(0x500) ++
// Example of empty list
Nil
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment