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MATANA
Matana on Chipyard
Commits
3ce18a13
Commit
3ce18a13
authored
Aug 30, 2021
by
Yuxiao Mao
Browse files
RegmapUtil: decrement now represent the event that decrement, insteed of direction of event
parent
56af5974
Changes
2
Hide whitespace changes
Inline
Side-by-side
src/main/scala/DetectPatternPrime.scala
View file @
3ce18a13
...
...
@@ -130,26 +130,24 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
// Attack Pattern
// Description: Mix pattern
// 1) count1, but decrement the counter by 1 if count_pack_valid reach thresh (0x800=2048) // TODO: perhaps adjust using dmemaddr / slow cycle count
// 1) = atk_prime_1, but decrement the counter by 1 if count_pack_valid reach thresh 0x800 (2048) // TODO: perhaps adjust using dmemaddr / slow cycle count
// 2) = atk_prime_1, but decrement the counter by 1 if count_pack_valid reach thresh 0x400 (1024)
val
c
ount
P
ack
V
alid
Thresh
=
0x800
L
//2048
// C
ount
p
ack
v
alid
for decrement counters
val
count_pack_valid
=
RegInit
(
0.
U
(
mp
.
counterWidth
.
W
)).
suggestName
(
"dpprime_count_pack_valid"
)
val
count_pack_valid_dec
=
RegInit
(
false
.
B
).
suggestName
(
"dpprime_count_pack_valid_dec"
)
when
(
in
.
resetCounters
)
{
count_pack_valid
:=
0.
U
count_pack_valid_dec
:=
false
.
B
}.
elsewhen
(
in
.
isMonitoring
)
{
when
(
count_pack_valid
=/=
countPackValidThresh
.
U
)
{
// count < thresh
count_pack_valid
:=
count_pack_valid
+
in
.
pack_has_valid
count_pack_valid_dec
:=
false
.
B
}.
otherwise
{
// count reach threshold
count_pack_valid
:=
0.
U
count_pack_valid_dec
:=
true
.
B
}
count_pack_valid
:=
count_pack_valid
+
in
.
pack_has_valid
}
val
atk_primemix_1
=
RegInit
(
false
.
B
)
atk_primemix_1
:=
Mux
(
count_pack_valid_dec
,
!
atk_prime_1
,
atk_prime_1
)
&&
in
.
isMonitoring
// if dec=true, dec1 if atk0, dec0 if atk1; if dec=false, inc1 if atk1, inc0 if atk0.
val
countPackValidThreshLengthMinus1_1
=
10
// Thresh = 2^(10+1) = 2048 = 0x800
val
countPackValidThreshLengthMinus1_2
=
9
// Thresh = 2^(9+1) = 1024 = 0x400
val
atk_prime_mix1_dec
=
RegInit
(
false
.
B
)
atk_prime_mix1_dec
:=
count_pack_valid
(
countPackValidThreshLengthMinus1_1
,
0
)
===
0.
U
val
atk_prime_mix2_dec
=
RegInit
(
false
.
B
)
atk_prime_mix2_dec
:=
count_pack_valid
(
countPackValidThreshLengthMinus1_2
,
0
)
===
0.
U
// Debug Signals
...
...
@@ -157,12 +155,12 @@ class DetectPatternPrimeInternal(params: DetectPatternPrimeParams)(implicit mp:
val
saved_addr0
=
RegInit
(
0.
U
(
mp
.
addrWidth
.
W
)).
suggestName
(
"saved_addr0"
)
saved_addr0
:=
Cat
(
saved_dmemtag
(
0
),
Cat
(
saved_dmemset
(
0
),
zeros_line
))
override
def
regmap
(
offset
:
Int
)
=
RegmapUtil
.
countEvent
(
atk_prime_1
,
in
.
resetCounters
,
offset
+
0x0
,
"AtkPrime1"
)
++
RegmapUtil
.
countEvent
(
atk_prime_2
,
in
.
resetCounters
,
offset
+
0x4
,
"AtkPrime2"
)
++
RegmapUtil
.
countEvent
(
atk_primeinst_1
,
in
.
resetCounters
,
offset
+
0x10
,
"AtkPrimeInst1"
)
++
RegmapUtil
.
countEventMax
(
atk_primemix_1
,
in
.
resetCounters
,
count_pack_valid_dec
,
offset
+
0x20
,
"AtkPrimeMix1"
)
++
RegmapUtil
.
countEventMax
(
atk_prime_1
,
in
.
resetCounters
,
atk_prime_mix1_dec
,
offset
+
0x20
,
"AtkPrimeMix1"
)
++
RegmapUtil
.
countEventMax
(
atk_prime_1
,
in
.
resetCounters
,
atk_prime_mix2_dec
,
offset
+
0x30
,
"AtkPrimeMix2"
)
++
Nil
}
...
...
src/main/scala/RegmapUtil.scala
View file @
3ce18a13
...
...
@@ -4,9 +4,9 @@ import chisel3._
import
freechips.rocketchip.regmapper.
{
RegField
,
RegFieldDesc
}
class
RegmapUtilCountEventIn
()(
implicit
val
mp
:
MatanaParams
)
extends
Bundle
{
val
event
=
Bool
()
val
event
=
Bool
()
// Event that increment counter
val
reset
=
Bool
()
val
decrement
=
Bool
()
val
decrement
=
Bool
()
// Event that decrement counter
}
class
RegmapUtilCountEvent
(
regName
:
String
)(
implicit
mp
:
MatanaParams
)
{
...
...
@@ -16,11 +16,11 @@ class RegmapUtilCountEvent(regName: String)(implicit mp: MatanaParams) {
when
(
in
.
reset
)
{
countEvent
:=
0.
U
}
.
otherwise
{
when
(
in
.
decrement
&&
in
.
event
)
{
when
(
in
.
event
&&
!
in
.
decrement
)
{
// Only inc
countEvent
:=
countEvent
+
1.
U
// TODO? increment should not overflow
}
.
elsewhen
(!
in
.
event
&&
in
.
decrement
)
{
// Only dec
countEvent
:=
Mux
(
countEvent
>=
1.
U
,
countEvent
-
in
.
event
,
0.
U
),
// decrement should not below 0
}
.
otherwise
{
countEvent
:=
countEvent
+
in
.
event
// TODO? increment should not overflow
}
}
// Else if inc and dec OR no inc no dec, should remain old value
}
// max: track count evolution when decrement exists
...
...
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