Commit 38de323a authored by Yuxiao Mao's avatar Yuxiao Mao
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README: add modify Matana section

parent ac03c31f
......@@ -87,15 +87,56 @@ Then regenerate Verilog by running `make verilog` in `Chipyard/sims/verilator`.
- `RocketDecode.scala`: some definitions in Rocket core that can help instruction decode.
- `AnalyzeInst.scala`: helper class that contains analysis of a single instruction.
- `RegmapUtil.scala`: helper class that contains generation of regmap information based on registers.
- `DetectExample.scala`: example class that contains the basic structure of a detection logic. If you want to add a new detection logic, you can refer to this class and where it is used.
- `DetectExample.scala`: example class that contains the basic structure of a detection logic.
- `DetectPattern*.scala`: detection logics.
- `subsystem/`: files unrelated to Matana module itself, but are used to improve/modify the original Chipyard.
- `board/`: Verilog files that helps to work in ML605 board.
- `bootrom/`: Bootrom program that will be included in Chipyard BootROM. Compared to Chipyard's version, it did not use wfi, and accept external interruption. If modified, you need to run `make` in this directory.
- `chipyard/`: contains patches made on the original Chipyard project.
- `chipyard/`: contains patches made on the original Chipyard project, patch and files are placed in there relative potition in Chipyard.
- `chipyard/generators/chipyard/src/main/scala/config/MatanaConfigs.scala` contains the Chipyard+Rocket config.
- `target/`: generated files by Chipyard build system.
- `build.sbt`: to integrate into Chipyard build system.
- ``: additional notes, including some problems encountered and their solution (if any).
# Modify Matana
Thanks to Chipyard ant Chisel, it is relatively simple to make change in the system, here is some indication in addition to what you can learn from project structure.
### Probed signal to Detection Module
A probe in Rocket Core is presented in current Matana project, files [<matana-chipyard>/chipyard/generators/rocket-chip/*](./chipyard/generators/rocket-chip). Where `MatanaCoreIO` correspond to probed signals IO, and `rocket-chip.patch` contains probed signals connected to IO and it path until leave tile (structure that contains a core and L1 cache etc).
From tile to Matana component, the connection is present in file [<matana-chipyard>/chipyard/chipyard.patch](./chipyard/chipyard.patch). It is prepared to handle multiples tiles.
### Detection Module: domain crossing
[<matana-chipyard>/src/main/scala/MatanaTop.scala](./src/main/scala/MatanaTop.scala) contains domain crossing, include clock divider, bus, interruption and dedicated connction crossing.
Bus and Interruption uses Chipyard's default crossing:
// TileLink and Interrupt nodes, (optional) crossing to slow clock domain
val node = if (params.log2ClockDiv == 0) matana_slow_detection.node else TLInwardCrossingHelper("matanaXbus", matana_slow_domain, matana_slow_detection.node)(AsynchronousCrossing())
val intnode = if (params.log2ClockDiv == 0) matana_slow_detection.intnode else IntOutwardCrossingHelper("matanaXint", matana_slow_domain, matana_slow_detection.intnode)(AsynchronousCrossing())
Dedicated connections uses crossing declared in [<matana-chipyard>/src/main/scala/MatanaSync.scala](./src/main/scala/MatanaSync.scala), named `seq2par` and `seq2one`. For example, the following code cross the signal `inst_valid` of all tiles in parallel connection to the slow clock domain:
``` { case (tile, i) =>
val matanaXdirect_fast_inst_valid = MatanaSync.seq2par(params.clockDiv, tile.inst_valid)
withClock(slow.clock) { := RegNext(RegNext(matanaXdirect_fast_inst_valid))
### Detection Module: new detection logic
1. Refer to [DetectExample.scala](./src/main/scala/DetectExample.scala) which contains a minimal blank logic that contains I/O, parameters, ourput regmap and some detection logics.
2. In [MatanaSlowDetection.scala](./src/main/scala/MatanaSlowDetection.scala), search location of `detectPatternTimer` for example to find where to add the detection logic, to connect I/O, put regmap with others regmap, etc.
3. In [Configs.scala](./src/main/scala/Configs.scala), similar to `dExample: Option[DetectExampleParams] = None, //Some(DetectExampleParams())`, use None if you do not want to include the new logic, use Some if you do want to include.
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