Commit 323cc023 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

Chipyard 1.5: various fix on Config, Class name. Dev stopped due to complex adaptation effort

parent e170c556
......@@ -59,7 +59,9 @@ git apply ../matana/chipyard/generators/sifive-cache/sifive-cache.patch
To use 32bit system:
1. (Rocket core) In `matana/chipyard/generators/chipyard/MatanaConfig.scala`, uncomment `new freechips.rocketchip.subsystem.WithRV32 ++`.
1. Coes:
- (Rocket core) In `matana/chipyard/generators/chipyard/MatanaConfig.scala`, uncomment `new freechips.rocketchip.subsystem.WithRV32 ++`.
Then regenerate verilog by running `make verilog` in `Chipyard/sims/verilator`.
- (Boom core) Does not seems to allow 32-bit core in the current version.
2. In `matana/board/BoardTop.v`, modify `localparam C_S_AXI_DATA_WIDTH = 64;` to 32.
......@@ -31,7 +31,7 @@ index 00000000..26515091
+../../../../matana/chipyard/generators/chipyard/ImplemTop.scala
\ No newline at end of file
diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index 93d7c237..77afe41f 100644
index 93d7c237..7818c8b1 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -24,6 +24,7 @@ import freechips.rocketchip.amba.axi4._
......@@ -50,7 +50,7 @@ index 93d7c237..77afe41f 100644
{
def coreMonitorBundles = tiles.map {
case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
@@ -78,11 +80,20 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
@@ -78,11 +80,23 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasTilesModuleImp
......@@ -63,9 +63,12 @@ index 93d7c237..77afe41f 100644
DromajoHelper.addArtefacts(InSubsystem)
+
+ // Optionally connect tiles to Matana module
+ // TODO: matana bug here with
+ // chisel3.internal.ChiselException: Connection between sink and source failed @: Sink or source unavailable to current module. (right side)
+ // Possible solution: refer to rocket-chip traceSourceNode, traceNode, connectOutputNotifications
+ _outer.matana match {
+ case Some(matana) => {
+ matana.module.io.tiles <> matana_tiles
+ matana.module.io.tiles <> _outer.tiles.map(_.module.matana_tile)
+ }
+ case None => None
+ }
......
......@@ -7,7 +7,6 @@ import chisel3._
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.devices.debug.Debug
import freechips.rocketchip.system.SimAXIMem
import sifive.blocks.devices.uart.{UARTPortIO, UARTParams}
import freechips.rocketchip.subsystem.NExtTopInterrupts
import freechips.rocketchip.amba.axi4.AXI4Bundle
......@@ -15,8 +14,17 @@ import freechips.rocketchip.amba.axi4.AXI4Bundle
// Adapt from chipyard & rocket-chip TestHarness
class ImplemTop()(implicit p: Parameters) extends Module {
val ldut = LazyModule(new DigitalTop)
val dut = Module(ldut.module)
val chipLazyDut = LazyModule(p(BuildTop)(p)).suggestName("chiptop")
val chipDut = Module(chipLazyDut.module)
val digitalLazyDut = chipLazyDut match {
case d: ChipTop => d.lazySystem
}
val ldut = digitalLazyDut match {
case d: DigitalTop => d
}
val dut = ldut.module
val io = IO(new Bundle {
val success = Output(Bool()) // emulator.cc want this port to be present
......@@ -34,17 +42,9 @@ class ImplemTop()(implicit p: Parameters) extends Module {
io.success := false.B
dut.dontTouchPorts()
dut.tieoffSerial()
// dut.tieoffSerial()
ldut.l2_frontend_bus_axi4.foreach(_.tieoff)
// Debug: tieoffDebug from firechip/BridgeBinders & chipyard/IOBinders
Debug.tieoffDebug(dut.debug, dut.resetctrl, Some(dut.psd))(dut.p)
dut.debug.foreach { d =>
d.clockeddmi.foreach({ cdmi => cdmi.dmi.req.bits := DontCare; cdmi.dmiClock := dut.clock })
d.dmactiveAck := DontCare
d.clock := dut.clock
}
// Mem asynchronous (DRAM):
dut.mem_clock := io.mem_clock
// TypeNote: ldut.mem_axi4(HeterogeneousBag[AXI4Bundle])
......
......@@ -2,7 +2,7 @@
package chipyard
import freechips.rocketchip.config.Config
import freechips.rocketchip.config.{Config}
import matana._
// --------------
......@@ -14,51 +14,47 @@ import matana._
class MatanaConfig extends Config(
new WithMatana ++
new matana.WithMatanaBootROM ++ // use custom simplified bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.harness.WithTiedOffDebug++ // no debug signal
new matana.WithEthernetAXI4Port ++ // master and slave port for ethernet
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithExtMemSize(0x20000000L) ++
new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
new freechips.rocketchip.subsystem.WithExtMemSize(0x20000000L) ++ // Use external memory
new freechips.rocketchip.subsystem.WithInclusiveCache(capacityKB=32) ++ // use Sifive L2 cache
new chipyard.config.WithL2TLBs(128) ++ // rocket & boom core: use L2 TLBs
new chipyard.config.WithRenumberHarts ++ // avoid hartid overlap when using different cores
// new WithBoomTile ++ // BOOM tile
new WithRocketTile ++ // Rocket tile
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new matana.WithPbusDTSFrequency(BigInt(50000000)) ++ // Was 100MHz, I dont know if that impact UART/Bus behavior
new freechips.rocketchip.subsystem.WithTimebase(BigInt(50000000)) ++ // 50 MHz
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
new chipyard.config.WithL2TLBs(128) ++ // use L2 TLBs
// BOOM CORE
// new boom.common.WithBoomBranchPrintf ++ // debug: branch predictor (if no debug commit)
// new boom.common.WithBoomCommitLogPrintf ++ // debug: commit
// new boom.common.WithNBoomPerfCounters ++ // perf counters?
// new boom.common.WithNSmallBooms(1) ++ // single boom-core, small core, decodeWidth=1, XLen=64 (does not support 32 bit)
class WithRocketTile(nCores: Int = 1) extends Config(
// new matana.WithBTB ++ // tile: use BTB
// new freechips.rocketchip.subsystem.WithL1DCacheSets(32) ++ // L1DCache: 32 sets
// new freechips.rocketchip.subsystem.WithL1DCacheWays(2) ++ // L1DCache: 2 ways
new matana.WithRocketCoreCFlush ++ // core: support for CFlush
// ROCKET CORE
// new freechips.rocketchip.subsystem.WithDefaultBTB ++ // tile: use BTB
// new matana.WithRocketCoreCFlush ++ // core: support for L1 CFlush
// new freechips.rocketchip.subsystem.WithRV32 ++ // set system to be 32-bit
// Small core does not work properly, it hang the simulation. Med or Big core is fine.
new freechips.rocketchip.subsystem.WithNMedCores(nCores) // single rocket-core, 64sets*1ways*64byte L1D/ICache
)
class WithBoomTile(nCores: Int = 1) extends Config(
new boom.common.WithBoomBranchPrintf ++ // debug: branch predictor (if no debug commit)
new boom.common.WithBoomCommitLogPrintf ++ // debug: commit
// Boom core has an error using RV32 even with chipyard basic boom config.
// new boom.common.WithoutBoomFPU ++ // no fp (rv32 does not support fp)
// new boom.common.WithBoomRV32 ++ // rv32 (32bit), set XLen=32
new boom.common.WithSmallBooms ++ // small core, decodeWidth=1, XLen=64
new boom.common.WithNBoomCores(nCores) // single boom-core
)
// In Chipyard 1.3.0, small core does not work properly, it hang the simulation. Med or Big core is fine.
new freechips.rocketchip.subsystem.WithNMedCores(1) ++ // single rocket-core, 64sets*1ways*64byte L1D/ICache
// Set system frequency to 50 MHz (the Config are basically the same in chipyard.config and freechips.rocketchip.subsystem.), MBus crossing managed in Async trait.
new chipyard.config.WithSystemBusFrequencyAsDefault ++
new chipyard.config.WithTileFrequency(50.0) ++
new chipyard.config.WithFrontBusFrequency(50.0) ++
new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.config.WithMemoryBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new freechips.rocketchip.subsystem.WithTimebase(BigInt(50000000)) ++ // 50 MHz, don't know if that useful
new chipyard.WithMulticlockCoherentBusTopology ++ // hierarchical buses including mbus+l2
new chipyard.config.AbstractConfig) // "base" rocketchip system
// Matana configuration that support simulation
// top file: chipyard.TestHarness
class MatanaHarnessConfig extends Config(
// chipyard.iobinders apply mostly only to chipyard.TestHarness
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.harness.WithUARTAdapter ++
new chipyard.harness.WithBlackBoxSimMem ++
new chipyard.harness.WithTieOffInterrupts ++
new chipyard.harness.WithSimSerial ++
new testchipip.WithDefaultSerialTL ++
new chipyard.config.WithBootROM ++
new MatanaConfig)
......@@ -18,17 +18,6 @@ index c202ca921..e7f530be8 100644
// gate the clock
val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0 || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc
when (unpause) { id_reg_pause := false }
diff --git a/src/main/scala/subsystem/HasTiles.scala b/src/main/scala/subsystem/HasTiles.scala
index cf6143498..647909605 100644
--- a/src/main/scala/subsystem/HasTiles.scala
+++ b/src/main/scala/subsystem/HasTiles.scala
@@ -432,4 +432,6 @@ trait HasTilesModuleImp extends LazyModuleImp with HasPeripheryDebugModuleImp {
}
}
val nmi = outer.tiles.zip(outer.tileNMIIONodes).zipWithIndex.map { case ((tile, n), i) => tile.tileParams.core.useNMI.option(n.makeIO(s"nmi_$i")) }
+
+ val matana_tiles = outer.tiles.map(_.module.matana_tile)
}
diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala
index 9651e352f..aee20447c 100644
--- a/src/main/scala/tile/BaseTile.scala
......
......@@ -4,11 +4,11 @@ import chisel3._
import chisel3.experimental.chiselName
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy.{AsynchronousCrossing, LazyModule, LazyModuleImp}
import freechips.rocketchip.interrupts.IntOutwardCrossingHelper
import freechips.rocketchip.interrupts.IntOutwardClockCrossingHelper
import freechips.rocketchip.prci.ClockSinkDomain
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.tile.MatanaCoreIO
import freechips.rocketchip.tilelink.TLInwardCrossingHelper
import freechips.rocketchip.tilelink.TLInwardClockCrossingHelper
// MatanaTop, connect cores to MatanaSlowDetection.
// Contains all cross clock domain connection (clock, TLbus, interrupts, direct sequential to parallel link) between the processor and MatanaSlowDetection module.
......@@ -28,8 +28,8 @@ class MatanaTopModule(params: MatanaParams, beatBytes: Int)(implicit p: Paramete
// TileLink and Interrupt crossing to slow clock domain
// Was RationalCrossing(SlowToFast), dont know if it is this element that cause Linux Kernel Freezing
val node = TLInwardCrossingHelper("matanaXbus", matana_slow_domain, matana_slow_detection.node)(AsynchronousCrossing())
val intnode = IntOutwardCrossingHelper("matanaXint", matana_slow_domain, matana_slow_detection.intnode)(AsynchronousCrossing())
val node = TLInwardClockCrossingHelper("matanaXbus", matana_slow_domain, matana_slow_detection.node)(AsynchronousCrossing())
val intnode = IntOutwardClockCrossingHelper("matanaXint", matana_slow_domain, matana_slow_detection.intnode)(AsynchronousCrossing())
}
@chiselName
......
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