Commit 1b69fbdc authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

Timer: use counter, up to 16x

parent c69f304a
package matana
import chisel3._
import chisel3.util.Cat
import chisel3.util.{Cat, log2Ceil}
import freechips.rocketchip.regmapper.RegField
case class DetectPatternTimerParams(
......@@ -33,41 +33,44 @@ class DetectPatternTimerInternal(params: DetectPatternTimerParams)(implicit mp:
// Registed (valid) pack analysis result for multiple slow cycles
val npackSize: Int = params.npackSizeInFastCycles / mp.clockDiv
val npackSize2: Int = npackSize * 2;
val npackSize4: Int = npackSize * 4;
val npackSize8: Int = npackSize * 8;
val npackSizeMax: Int = npackSize * 16;
val npack_timer = RegInit(0.U(npackSize8.W)).suggestName("npack_timer")
val npack_timer_orR = RegInit(false.B)
val npack_timer_orR2 = RegInit(false.B)
val npack_timer_orR4 = RegInit(false.B)
val npack_timer_orR8 = RegInit(false.B)
when (in.pack_has_valid) {
npack_timer := Cat(npack_timer(npackSize8-2, 0), in.pack_has_timer)
npack_timer_orR := npack_timer(npackSize-2, 0).orR || in.pack_has_timer
npack_timer_orR2 := npack_timer(npackSize2-2, 0).orR || in.pack_has_timer
npack_timer_orR4 := npack_timer(npackSize4-2, 0).orR || in.pack_has_timer
npack_timer_orR8 := npack_timer(npackSize8-2, 0).orR || in.pack_has_timer
val last_timer_count = RegInit(0.U((log2Ceil(npackSizeMax) + 1).W)).suggestName("last_timer_count")
val last_timer_in_window = RegInit(false.B).suggestName("last_timer_in_window")
when (in.resetCounters) {
last_timer_count := 0.U
last_timer_in_window := false.B
} .elsewhen (in.isMonitoring && in.pack_has_valid) {
when (in.pack_has_timer) {
last_timer_count := 0.U
last_timer_in_window := true.B
}.otherwise {
last_timer_count := last_timer_count + 1.U
last_timer_in_window := Mux(last_timer_in_window && (last_timer_count >= npackSizeMax.U), false.B, last_timer_in_window)
}
}
val atk_timer_timer = Wire(Bool())
val atk_timer_timer2 = Wire(Bool())
val atk_timer_timer4 = Wire(Bool())
val atk_timer_timer8 = Wire(Bool())
atk_timer_timer := npack_timer_orR && in.pack_has_timer && in.isMonitoring
atk_timer_timer2 := npack_timer_orR2 && in.pack_has_timer && in.isMonitoring
atk_timer_timer4 := npack_timer_orR4 && in.pack_has_timer && in.isMonitoring
atk_timer_timer8 := npack_timer_orR8 && in.pack_has_timer && in.isMonitoring
val atk_timer_timer16 = Wire(Bool())
atk_timer_timer := last_timer_in_window && (last_timer_count <= npackSize.U) && in.pack_has_timer && in.isMonitoring
atk_timer_timer2 := last_timer_in_window && (last_timer_count <= (npackSize*2).U) && in.pack_has_timer && in.isMonitoring
atk_timer_timer4 := last_timer_in_window && (last_timer_count <= (npackSize*4).U) && in.pack_has_timer && in.isMonitoring
atk_timer_timer8 := last_timer_in_window && (last_timer_count <= (npackSize*8).U) && in.pack_has_timer && in.isMonitoring
atk_timer_timer16 := last_timer_in_window && (last_timer_count <= (npackSize*16).U) && in.pack_has_timer && in.isMonitoring
val atk_timer_flush = Wire(Bool())
atk_timer_flush := npack_timer_orR && in.pack_has_flush && in.isMonitoring
atk_timer_flush := last_timer_in_window && (last_timer_count <= npackSize.U) && in.pack_has_flush && in.isMonitoring
override def regmap(offset: Int) =
(if (params.withTimerTimer) {
RegmapUtil.countEventThreshAlarm(atk_timer_timer, in.resetCounters, offset, "AtkTimerTimer") ++
RegmapUtil.countEvent(atk_timer_timer2, in.resetCounters, offset + 0x10, "AtkTimerTimer2") ++
RegmapUtil.countEvent(atk_timer_timer4, in.resetCounters, offset + 0x14, "AtkTimerTimer4") ++
RegmapUtil.countEvent(atk_timer_timer8, in.resetCounters, offset + 0x18, "AtkTimerTimer8")
RegmapUtil.countEvent(atk_timer_timer8, in.resetCounters, offset + 0x18, "AtkTimerTimer8") ++
RegmapUtil.countEvent(atk_timer_timer8, in.resetCounters, offset + 0x20, "AtkTimerTimer16")
} else Nil) ++
(if (params.withTimerFlush) {
RegmapUtil.countEventThreshAlarm(atk_timer_flush, in.resetCounters, offset + 0x80, "AtkTimerFlush")
......
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