Commit 0cada9c0 authored by Yuxiao Mao's avatar Yuxiao Mao
Browse files

Detect Input: add performance counters from rocket core

parent 1a518fb8
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
index c6d86ce5f..301c90c24 100644
index c6d86ce5f..99d98c9fc 100644
--- a/src/main/scala/rocket/RocketCore.scala
+++ b/src/main/scala/rocket/RocketCore.scala
@@ -846,6 +846,16 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
@@ -846,6 +846,20 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p)
io.rocc.cmd.bits.rs1 := wb_reg_wdata
io.rocc.cmd.bits.rs2 := wb_reg_rs2
......@@ -15,6 +15,10 @@ index c6d86ce5f..301c90c24 100644
+ // dmem access is at ex stage
+ io.matana.dmemaddr_data := encodeVirtualAddress(ex_rs(0), alu.io.adder_out) // copy from io.dmem.req.bits.addr
+ io.matana.dmemaddr_valid := ex_reg_valid && ex_ctrl.mem
+ // performance counters
+ io.matana.hpc.dcache_miss := io.dmem.perf.acquire
+ io.matana.hpc.dcache_release := io.dmem.perf.release
+ io.matana.hpc.branch_mispredict := take_pc_mem && mem_direction_misprediction
+
// gate the clock
val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0 || io.dmem.perf.release || take_pc
......
......@@ -12,4 +12,11 @@ class MatanaCoreIO extends Bundle {
val pc_valid = Output(Bool())
val dmemaddr_data = Output(UInt(40.W)) // used by DCacheMetadataReq
val dmemaddr_valid = Output(Bool())
val hpc = new MatanaCoreHpcIO()
}
class MatanaCoreHpcIO extends Bundle {
val dcache_miss = Output(Bool())
val dcache_release = Output(Bool())
val branch_mispredict = Output(Bool())
}
......@@ -5,6 +5,7 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, SimpleDevice, AddressSet, Resource}
import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldRdAction}
import freechips.rocketchip.tile.MatanaCoreHpcIO
import freechips.rocketchip.tilelink.TLRegisterNode
// MatanaSlowDetection, work in a single slow clock domain.
......@@ -35,6 +36,8 @@ class MatanaDetectionPerCoreIO()(implicit val mp: MatanaParams) extends Bundle {
val one_pc_valid = Input(Bool())
val one_dmemaddr_data = Input(UInt(mp.addrWidth.W))
val one_dmemaddr_valid = Input(Bool())
// Performance counters
val vec_hpc = Input(Vec(mp.clockDiv, new MatanaCoreHpcIO()))
}
class MatanaSlowDetectionImp(outer: MatanaSlowDetection, params: MatanaParams)
......
......@@ -54,6 +54,7 @@ class MatanaTopModuleImp(outer: MatanaTopModule, params: MatanaParams)
val matanaXdirect_fast_inst_valid = MatanaSync.seq2par(params.clockDiv, tile.inst_valid)
val (matanaXdirect_fast_pc_data, matanaXdirect_fast_pc_valid) = MatanaSync.seq2one(params.clockDiv, tile.pc_data, tile.pc_valid)
val (matanaXdirect_fast_dmemaddr_data, matanaXdirect_fast_dmemaddr_valid) = MatanaSync.seq2one(params.clockDiv, tile.dmemaddr_data, tile.dmemaddr_valid)
val matanaXdirect_fast_hpc = MatanaSync.seq2par(params.clockDiv, tile.hpc)
// Registered at slow side
// We do not need AsyncQueue that introduce higher latency and resources usages, as we are sure that receiver is always ready and sender is always valid
withClock(slow.clock) {
......@@ -63,6 +64,7 @@ class MatanaTopModuleImp(outer: MatanaTopModule, params: MatanaParams)
detection.io.packs(i).one_pc_valid := RegNext(RegNext(matanaXdirect_fast_pc_valid))
detection.io.packs(i).one_dmemaddr_data := RegNext(RegNext(matanaXdirect_fast_dmemaddr_data))
detection.io.packs(i).one_dmemaddr_valid := RegNext(RegNext(matanaXdirect_fast_dmemaddr_valid))
detection.io.packs(i).vec_hpc := RegNext(RegNext(matanaXdirect_fast_hpc))
}
}
}
......
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