Commit 18ee577b authored by Jean Alinei's avatar Jean Alinei
Browse files

Merge branch 'actualV0.9' into 'master'

V0.9 Release

See merge request owntech/1leg!2
parents 8515832c 5743d783
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D_Schottky
#
DEF Device_D_Schottky D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_D_Schottky" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 0 50 0 -50 0 N
P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
P 6 0 1 10 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_Small
#
DEF Device_R_Small R 0 10 N N 1 F N
F0 "R" 30 20 50 H V L CNN
F1 "Device_R_Small" 30 -40 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -30 70 30 -70 0 1 8 N
X ~ 1 0 100 30 D 50 50 1 1 P
X ~ 2 0 -100 30 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Driver_FET_UCC21520DW
#
DEF Driver_FET_UCC21520DW U 0 20 Y Y 1 F N
F0 "U" 0 650 50 H V C CNN
F1 "Driver_FET_UCC21520DW" 0 550 50 H V C CNN
F2 "Package_SO:SOIC-16W_7.5x10.3mm_P1.27mm" 0 -550 50 H I C CNN
F3 "" 0 -50 50 H I C CNN
ALIAS UCC21520ADW
$FPLIST
SOIC*7.5x10.3mm*P1.27mm*
$ENDFPLIST
DRAW
T 900 -130 0 25 0 0 0 "Logic Input" Normal 0 C C
S 40 -250 -40 -350 0 0 0 N
S 40 350 -40 250 0 0 0 N
S -150 450 -100 -450 0 1 0 N
S 400 500 -400 -500 0 1 0 f
P 2 0 0 0 -25 250 -25 200 N
P 2 0 0 0 -25 400 -25 350 N
P 2 0 0 0 -25 475 -25 425 N
P 2 0 0 0 -10 -300 -100 -300 N
P 2 0 0 10 -10 -270 -10 -330 N
P 2 0 0 0 -10 300 -100 300 N
P 2 0 0 10 -10 330 -10 270 N
P 2 0 0 0 10 -300 70 -300 N
P 2 0 0 10 10 -270 10 -330 N
P 2 0 0 0 10 300 70 300 N
P 2 0 0 10 10 330 10 270 N
P 2 0 0 0 25 250 25 200 N
P 2 0 0 0 25 350 25 400 N
P 2 0 0 0 25 425 25 475 N
P 2 0 0 0 100 -25 50 -25 N
P 2 0 0 0 100 25 50 25 N
P 2 0 0 0 160 -300 130 -300 N
P 2 0 0 0 160 300 130 300 N
P 2 0 0 0 175 -25 125 -25 N
P 2 0 0 0 175 25 125 25 N
P 2 0 0 0 250 -25 200 -25 N
P 2 0 0 0 250 25 200 25 N
P 2 0 0 0 325 -25 275 -25 N
P 2 0 0 0 325 25 275 25 N
P 2 0 0 0 400 -25 350 -25 N
P 2 0 0 0 400 25 350 25 N
P 3 0 0 0 160 -400 100 -400 100 -330 N
P 3 0 0 0 160 -200 100 -200 100 -270 N
P 3 0 0 0 160 200 100 200 100 270 N
P 3 0 0 0 160 400 100 400 100 330 N
P 4 0 0 0 130 -300 70 -360 70 -240 130 -300 N
P 4 0 0 0 130 300 70 240 70 360 130 300 N
P 2 0 1 0 -150 -400 -180 -400 N
P 2 0 1 0 -150 -300 -180 -300 N
P 2 0 1 0 -150 -100 -180 -100 N
P 2 0 1 0 -150 0 -180 0 N
P 2 0 1 0 -150 100 -180 100 N
P 2 0 1 0 -150 400 -180 400 N
P 2 0 1 0 -25 -425 -25 -475 N
P 2 0 1 0 -25 -350 -25 -400 N
P 2 0 1 0 -25 -200 -25 -250 N
P 2 0 1 0 -25 -125 -25 -175 N
P 2 0 1 0 -25 -50 -25 -100 N
P 2 0 1 0 -25 25 -25 -25 N
P 2 0 1 0 -25 100 -25 50 N
P 2 0 1 0 -25 175 -25 125 N
P 2 0 1 0 25 -425 25 -475 N
P 2 0 1 0 25 -350 25 -400 N
P 2 0 1 0 25 -200 25 -250 N
P 2 0 1 0 25 -125 25 -175 N
P 2 0 1 0 25 -50 25 -100 N
P 2 0 1 0 25 25 25 -25 N
P 2 0 1 0 25 100 25 50 N
P 2 0 1 0 25 175 25 125 N
X INA 1 -500 100 100 R 50 50 1 1 I
X OUTB 10 500 -300 100 L 50 50 1 1 O
X VDDB 11 500 -200 100 L 50 50 1 1 W
X NC 12 400 -100 100 L 50 50 1 1 N N
X NC 13 400 100 100 L 50 50 1 1 N N
X VSSA 14 500 200 100 L 50 50 1 1 W
X OUTA 15 500 300 100 L 50 50 1 1 O
X VDDA 16 500 400 100 L 50 50 1 1 W
X INB 2 -500 0 100 R 50 50 1 1 I
X VCCI 3 -500 400 100 R 50 50 1 1 W
X GND 4 -500 -400 100 R 50 50 1 1 W
X DIS 5 -500 -100 100 R 50 50 1 1 I
X DT 6 -500 -300 100 R 50 50 1 1 P
X NC 7 -400 -200 100 R 50 50 1 1 N N
X VCCI 8 -500 400 100 R 50 50 1 1 P N
X VSSB 9 500 -400 100 L 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Isolator_SFH617A-2X009T
#
DEF Isolator_SFH617A-2X009T U 0 20 Y Y 1 F N
F0 "U" -150 200 50 H V C CNN
F1 "Isolator_SFH617A-2X009T" 0 -200 50 H V C CNN
F2 "Package_DIP:SMDIP-4_W7.62mm" 0 -300 50 H I C CNN
F3 "" -350 300 50 H I C CNN
ALIAS SFH617A-2X019T
$FPLIST
SMDIP*W7.62mm*
$ENDFPLIST
DRAW
S -200 150 200 -150 1 1 10 f
P 2 1 1 10 -125 -25 -75 -25 N
P 2 1 1 0 100 25 175 100 N
P 2 1 1 0 175 -100 100 -25 F
P 2 1 1 0 175 -100 200 -100 N
P 2 1 1 0 175 100 200 100 N
P 3 1 1 0 -200 100 -100 100 -100 -30 N
P 3 1 1 0 -100 -25 -100 -100 -200 -100 N
P 3 1 1 20 100 75 100 -75 100 -75 N
P 4 1 1 10 -100 -25 -125 25 -75 25 -100 -25 N
P 5 1 1 0 -20 -20 30 -20 15 -25 15 -15 30 -20 N
P 5 1 1 0 -20 20 30 20 15 15 15 25 30 20 N
P 5 1 1 0 120 -65 140 -45 160 -85 120 -65 120 -65 F
X ~ 1 -300 100 100 R 50 50 1 1 P
X ~ 2 -300 -100 100 R 50 50 1 1 P
X ~ 3 300 -100 100 L 50 50 1 1 P
X ~ 4 300 100 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Symbols_Driver_stage_outline_inputs
#
DEF Symbols_Driver_stage_outline_inputs J 0 40 Y Y 1 F N
F0 "J" 0 0 50 H V C CNN
F1 "Symbols_Driver_stage_outline_inputs" 100 0 50 H V C CNN
F2 "Footprints:Driver_stage_outline_inputs" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S 850 450 400 100 0 0 0 N
S 850 450 450 150 0 0 0 N
S -800 450 850 -600 0 1 0 N
X 15V 1 950 350 100 L 50 50 1 1 W
X GNDREF 2 950 250 100 L 50 50 1 1 W
X PWM_H1 3 -900 250 100 R 50 50 1 1 I
X PWM_L1 4 -900 150 100 R 50 50 1 1 I
X PWM_H2 5 -900 -250 100 R 50 50 1 1 I
X PWM_L2 6 -900 -350 100 R 50 50 1 1 I
X N_GND_CMD 7 -900 -450 100 R 50 50 1 1 I
X +5VD 8 -900 -550 100 R 50 50 1 1 W
X +5VD 8 -900 50 100 R 50 50 1 1 W
X DGND 9 -900 -150 100 R 50 50 1 1 I
X DGND 9 -900 350 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# Symbols_Driver_stage_outline_outputs
#
DEF Symbols_Driver_stage_outline_outputs J 0 40 Y Y 1 F N
F0 "J" 250 -950 50 H V C CNN
F1 "Symbols_Driver_stage_outline_outputs" 500 -1100 50 H V C CNN
F2 "Footprints:Driver_stage_outline_outputs" 500 -650 50 H V C CNN
F3 "" 250 -950 50 H I C CNN
DRAW
T 0 550 500 50 0 0 0 "From/To Power stage" Normal 0 C C
S -900 1150 50 -1350 0 0 0 N
S 1000 1150 50 -550 0 0 0 N
S -900 1150 1000 -1350 0 1 0 N
X GND 19 1100 1000 100 L 50 50 1 1 B
X PWM_L2 20 1100 900 100 L 50 50 1 1 O
X SW_Node2 21 1100 800 100 L 50 50 1 1 I
X PWM_H2 22 1100 700 100 L 50 50 1 1 O
X GND 23 1100 300 100 L 50 50 1 1 B
X PWM_L1 24 1100 200 100 L 50 50 1 1 O
X SW_Node1 25 1100 100 100 L 50 50 1 1 I
X PWM_H1 26 1100 0 100 L 50 50 1 1 O
X Neutral_GND_cmd 27 1100 -250 100 L 50 50 1 1 O
X GND 28 1100 -350 100 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# power_+15V
#
DEF power_+15V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+15V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +15V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5VD
#
DEF power_+5VD #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5VD" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5VD 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GNDD
#
DEF power_GNDD #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GNDD" 0 -125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -50 -60 50 -80 0 1 10 F
P 2 0 1 0 0 0 0 -60 N
X GNDD 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GNDREF
#
DEF power_GNDREF #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GNDREF" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -25 -75 25 -75 N
P 2 0 1 0 -5 -100 5 -100 N
P 2 0 1 0 0 -50 0 0 N
P 2 0 1 0 50 -50 -50 -50 N
X GNDREF 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library
EESchema-DOCLIB Version 2.0
#
#End Doc Library
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Board_outline-symbols
#
DEF Board_outline-symbols J 0 40 Y Y 1 F N
F0 "J" 250 -950 50 H V C CNN
F1 "Board_outline-symbols" 500 -1100 50 H V C CNN
F2 "Footprints:Board outline" 500 -650 50 H V C CNN
F3 "" 250 -950 50 H I C CNN
DRAW
T 0 -300 100 50 0 0 0 From/To Normal 0 C C
T 0 550 500 50 0 0 0 "From/To Driver stage" Normal 0 C C
T 0 -350 0 50 0 0 0 "Measurment stage" Normal 0 C C
S -900 1150 50 -1350 0 0 0 N
S 1000 1150 50 -550 0 0 0 N
S -900 1150 1000 -1350 0 1 0 N
X D5V 1 -1000 1050 100 R 50 50 1 1 W
X VIHigh+ 10 -1000 -150 100 R 50 50 1 1 B
X VIHigh- 11 -1000 -250 100 R 50 50 1 1 B
X VILow1+ 12 -1000 -450 100 R 50 50 1 1 B
X VILow1- 13 -1000 -550 100 R 50 50 1 1 B
X VILow2+ 14 -1000 -750 100 R 50 50 1 1 B
X VILow2- 15 -1000 -850 100 R 50 50 1 1 B
X D5V 16 -1000 -1050 100 R 50 50 1 1 W
X VTh 17 -1000 -1150 100 R 50 50 1 1 B
X DGND 18 -1000 -1250 100 R 50 50 1 1 B
X GND 19 1100 1000 100 L 50 50 1 1 B
X IILow1 2 -1000 950 100 R 50 50 1 1 B
X PWM_L2 20 1100 900 100 L 50 50 1 1 B
X SW_Node2 21 1100 800 100 L 50 50 1 1 B
X PWM_H2 22 1100 700 100 L 50 50 1 1 B
X GND 23 1100 300 100 L 50 50 1 1 B
X PWM_L1 24 1100 200 100 L 50 50 1 1 B
X SW_Node1 25 1100 100 100 L 50 50 1 1 B
X PWM_H1 26 1100 0 100 L 50 50 1 1 B
X Neutral_GND_cmd 27 1100 -250 100 L 50 50 1 1 B
X GND 28 1100 -350 100 L 50 50 1 1 B
X DGND 3 -1000 850 100 R 50 50 1 1 B
X D5V 4 -1000 650 100 R 50 50 1 1 W
X IILow2 5 -1000 550 100 R 50 50 1 1 B
X DGND 6 -1000 450 100 R 50 50 1 1 B
X D5V 7 -1000 300 100 R 50 50 1 1 W
X IIHigh 8 -1000 200 100 R 50 50 1 1 B
X DGND 9 -1000 100 100 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
#End Library
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update=ven. 28 août 2020 10:31:38
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=Title_block.kicad_wks
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=Title_block.kicad_wks
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=1
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
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CopperTextSizeV=1.5
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OthersTextSizeH=1
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OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.05
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
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[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
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[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
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[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
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[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
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[pcbnew/Layer.F.Paste]
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[pcbnew/Layer.B.SilkS]
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[pcbnew/Layer.F.SilkS]
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[pcbnew/Layer.B.Mask]
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[pcbnew/Layer.F.Mask]
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[pcbnew/Layer.Dwgs.User]
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[pcbnew/Layer.Cmts.User]
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[pcbnew/Layer.Eco1.User]
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[pcbnew/Layer.Eco2.User]
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[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
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[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
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[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1