Commit 18ee577b authored by Jean Alinei's avatar Jean Alinei
Browse files

Merge branch 'actualV0.9' into 'master'

V0.9 Release

See merge request owntech/1leg!2
parents 8515832c 5743d783
**/*.bak
**/*.sch-bak
**/*.err
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update=lun. 27 juil. 2020 14:28:59
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[schematic_editor]
version=1
PageLayoutDescrFile=Title_block.kicad_wks
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=Title_block.kicad_wks
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.09999999999999999
CourtyardLineWidth=0.12
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=1
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
Sheet 1 4
Title "1Leg prototype"
Date "20/04/15"
Rev "-"
Comp "https://redmine.laas.fr/laas/owntech-5-phase-board.git"
Comment1 "ALINEI"
Comment2 "VILLA"
Comment3 "VILLA"
Comment4 "PREL"
$EndDescr
$Sheet
S 3750 2750 2550 2300
U 5E9B5CA6
F0 "Measurments" 138
F1 "Measurments.sch" 138
F2 "V_Th" I R 6300 4450 50
F3 "Iout_raw" I R 6300 4600 50
F4 "Iin_raw" I R 6300 4300 50
F5 "GND_opamp" I L 3750 3900 50
F6 "VAC_opamp" I L 3750 4050 50
F7 "VDC_opamp" I L 3750 4200 50
$EndSheet
$Sheet
S 3750 7900 2550 1750
U 5E99427A
F0 "Power" 138
F1 "Power.sch" 138
F2 "V_Th" I R 6300 8400 50
F3 "Iout_raw" I R 6300 8500 50
F4 "Iin_raw" I R 6300 8300 50
F5 "V_In" I L 3750 8350 50
F6 "V_Out" I L 3750 8450 50
F7 "PWM_Hi" I L 3750 8950 50
F8 "PWM_Lo" I L 3750 9050 50
$EndSheet
$Sheet
S 3750 5550 2550 1750
U 5E9944F3
F0 "Driver" 138
F1 "Driver.sch" 138
F2 "V_Th" I R 6300 7100 50
F3 "Iout_raw" I R 6300 7200 50
F4 "Iin_raw" I R 6300 7000 50
F5 "V_In" I L 3750 7150 50
F6 "V_Out" I L 3750 7050 50
F7 "PWM_Hi" I L 3750 6650 50
F8 "PWM_Lo" I L 3750 6500 50
F9 "PWM_Hi_cmd" I R 6300 5900 50
F10 "PWM_Lo_cmd" I R 6300 6000 50
F11 "N_GND_cmd" I R 6300 6100 50
F12 "GND_opamp" I L 3750 5850 50
F13 "VAC_opamp" I L 3750 6000 50
F14 "VDC_opamp" I L 3750 6150 50
$EndSheet
Wire Wire Line
6300 8300 6600 8300
Wire Wire Line
6300 8400 6600 8400
Wire Wire Line
6300 8500 6600 8500
Entry Wire Line
6700 7300 6600 7200
Entry Wire Line
6700 7200 6600 7100
Entry Wire Line
6700 7100 6600 7000
Wire Wire Line
6300 7000 6600 7000
Wire Wire Line
6300 7100 6600 7100
Wire Wire Line
6300 7200 6600 7200
Entry Wire Line
6600 8300 6700 8200
Entry Wire Line
6600 8400 6700 8300
Entry Wire Line
6600 8500 6700 8400
Entry Wire Line
6700 4700 6600 4600
Entry Wire Line
6700 4550 6600 4450
Entry Wire Line
6700 4400 6600 4300
Wire Wire Line
6300 4300 6600 4300
Wire Wire Line
6300 4450 6600 4450
Wire Wire Line
6300 4600 6600 4600
Wire Wire Line
3750 6150 3250 6150
Entry Wire Line
3150 6050 3250 6150
Wire Wire Line
3750 6000 3250 6000
Entry Wire Line
3150 5900 3250 6000
Wire Wire Line
3750 5850 3250 5850
Entry Wire Line
3150 5750 3250 5850
Wire Wire Line
3750 3900 3250 3900
Entry Wire Line
3150 4000 3250 3900
Wire Wire Line
3750 4050 3250 4050
Entry Wire Line
3150 4150 3250 4050
Wire Wire Line
3750 4200 3250 4200
Entry Wire Line
3150 4300 3250 4200
Wire Wire Line
3750 8350 3250 8350
Wire Wire Line
3750 8450 3250 8450
Entry Wire Line
3250 8350 3150 8250
Entry Wire Line
3250 8450 3150 8350
Wire Wire Line
3750 8950 3250 8950
Wire Wire Line
3750 9050 3250 9050
Entry Wire Line
3250 8950 3150 8850
Entry Wire Line
3250 9050 3150 8950
Wire Wire Line
3750 7150 3250 7150
Wire Wire Line
3750 7050 3250 7050
Entry Wire Line
3250 7150 3150 7250
Entry Wire Line
3250 7050 3150 7150
Wire Wire Line
3750 6650 3250 6650
Wire Wire Line
3750 6500 3250 6500
Entry Wire Line
3250 6650 3150 6750
Entry Wire Line
3250 6500 3150 6600
Wire Bus Line
3150 4000 3150 6050
Wire Bus Line
3150 6600 3150 8950
Wire Bus Line
6700 4400 6700 8400
$EndSCHEMATC
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